MODEL QUESTION PAPER-1 6.

Write any 4 Micro Operations

R1R2+R3
DR<- M [AR]
SECTION A (2 marks each Answer any 4) R1shl R2
1. Define computer Architecture. M [AR] <- R1
A: Computer Architecture is the combination of the computer
structure and behaviour as seen by the programmer that uses SECTION B (5 MARKS QUESTION answer any 4)
machine language instructions.
Computer Architecture=Machine Organization+ Instruction set 7. Simplify F(A,B,C,D)=∑(1,2,4,6,8,10,12,14) and draw a circuit
Architecture diagram.

2. Convert 782.4310 to binary 8. Define Half Adder and Draw the truth table and logic diagram
for the same
3. State DeMorgan’s Theorems Half adder is a combinational arithmetic circuit that adds two
Theorem1: The compliment of a product of variables is equal to numbers and produces a sum bit (s) and carry bit (c) both as
the sum of the complement f the individual variables output.
Truth table
Theorem 2: The compliment of a sum of variables is equal to
the product of the compliments of the individual variables.

4. Explain ION,IOF,SZA,STA instructions

ION: Interrupt ON,Sets an interrupt enable flip flop
Circuit diagram:
IOF: Interrupt OFF,Clears an interrupt enable flip flop
SZA: Skip next instruction if AC = 0
STA: Store AC content in memory

5. Define Cache Memory

Cache memory is an extremely fast memory type that acts as a
buffer between RAM and the CPU. It holds frequently
requested data and instructions so that they are immediately
available to the CPU when needed. The Boolean expressions for the SUM and CARRY outputs are
given by
 SUM=A XOR B o The Temporary Register (TR) is used for holding the temporary
CARRY= A.B data during the processing.
o The Input Registers (IR) holds the input characters given by the
[Link] the Different registers in basic computer. user.
Following are the Different Registers in basic computer: o The Output Registers (OR) holds the output after processing the
input data.
Register Symbol Number of bits Function

Data register DR 16 Holds memory operand

[Link] various addressing modes.
Address register AR 12 Holds address for the memory • Implied / Implicit Addressing Mode: In this mode the operand
is specified implicitly in the definition of the instruction.
Accumulator AC 16 Processor register
• Immediate Addressing Mode: In this mode, the operand is
Instruction register IR 16 Holds instruction code specified in the instruction itself.
• Direct Addressing Mode: In this mode, effective address of
Program counter PC 12 Holds address of the instruction operand is present in instruction itself.
Temporary register TR 16 Holds temporary data • Indirect Addressing Mode: In this, the address field of
instruction gives the address where the effective address is
Input register INPR 8 Carries input character stored in memory.
• Register Addressing Mode: In this mode, the register may
Output register OUTR 8 Carries output character
contain source operand, destination operand, or both.
• Register indirect Addressing Mode: In this mode the data to
be operated upon is available inside the memory location
o The Data Register (DR) contains 16 bits which hold the operand and this memory location is indirectly specified by a Register
read from the memory location. pair.
o The Memory Address Register (MAR) contains 12 bits which hold • Relative Addressing Mode: In this addressing mode, Effective
the address for the memory location. address of the operand is obtained by adding the content of
o The Program Counter (PC) also contains 12 bits which hold the program counter with the address part of the instruction.
address of the next instruction to be read from memory after the • Indexed Addressing Mode: In this addressing mode, Effective
current instruction is executed. address of the operand is obtained by adding the content of
index register with the address part of the instruction.
o The Accumulator (AC) register is a general purpose processing
• Base Register Addressing Mode: In this addressing mode,
register.
Effective address of the operand is obtained by adding the
o The instruction read from memory is placed in the Instruction content of base register with the address part of the
register (IR). instruction.
 • Auto-Increment/ Auto-Decrement Addressing Mode: In this • A 4 x 1multiplexer at the output chooses between an
addressing mode, After accessing the operand, the content of arithmetic output in Di and a logic output in Ei. The data in
the register is automatically incremented or decremented. the multiplexer are selected with inputs S3and S2. The
other two data inputs to the multiplexer receive inputs Ai -
[Link] Hardware Implementation of Shift Micro 1 forthe shift-right operation and Ai + 1 for the shift-left
Operations operation.
The arithmetic, logic, and shift circuits can be combined into one ALU • The circuit whose one stage is specified in image provides eight
with common selection variables. One stage of an arithmetic logic arithmetic operation, four logic operations, and two shift
shift unit is shown in the image below. The subscript i designates a operations. Each operation is selected with the five variables S3,
typical stage. Inputs Ai and Bi are applied to S2, S1, S0, and Cin The input carry Cin is used for selecting an
both the arithmetic and logic units. arithmetic operation only.
• Table lists the 14 operations of the ALU. The first eight are
arithmetic
operations and are selected with S3 S2 = 00. The next four are
logic operations and are selected with S3S2 = 01. The input carry
has no effect during the logic operations and is marked with
don't-care x's. The last two operations are shift operations and
are selected with S3S2 = 10 and 11. The other three selection
inputs have no effect on the shift.

12. Write the characteristics of multiprocessors.

the major characteristics of multiprocessors are as follows −
• Parallel Computing − Processors are identical and they work
together in such a way that the users are under the impression
that they are the only users of the system. In reality, however,
many users are accessing the system at a given time.
• Distributed Computing − This involves the usage of a network
of processors. Each processor in this network can be considered
as a computer in its own right and have the capability to solve a
problem.

• A particular microoperation is selected with inputs S1 and

S0.
• Supercomputing − This involves the usage of the fastest
machines to resolve big and computationally complex
problems.
• Pipelining − This is a method wherein a specific task is divided
into several subtasks that must be performed in a sequence.
The functional units help in performing each subtask. The units
are attached serially and all the units work simultaneously.
• Vector Computing − It involves the usage of vector processors,
wherein operations such as ‘multiplication’ are divided into
many steps and are then applied to a stream of operands
(“vectors”).
• Systolic − This is similar to pipelining, but units are not arranged
in a linear order. The steps in systolic are normally small and
more in number and performed in a lockstep manner.

SECTION C (8 MARKS EACH Answer any 4)

[Link] a sequential circuit for a 2 bit binary counter

• A binary counter is a 2MOD counter which counts upto 2 bits
state values. i.e 22 =4 values.
• The flip flops having a similar condition for toggling like T flip
flop and JK are used to construct the binary Counter.
• In the circuit design of the counter 2 JK flip flops are used. [Link] is a flip flops? Explain the Different types of Flip
• The high voltage signal is passed to the inputs of both flip flops Flops
• This high voltage inputs maintains the flip flops at a state 1 A flip flop is an electronic circuit with two stable states that can be
• The outputs Q0 and Q1 are the LSB and MSB bits, respectively. used to store binary data.
The truth table of JK flip flop helps us to understand the The flip flops are the fundamental building blocks of the digital
functioning of the counter. system.
• The output of the first flip flop passes to the second flip flop as A basic flip-flop can be constructed using four-NAND or four-NOR
a clock pulse. The counter counts the values 00, 01, 10, 11. gates.
After counting these values, the counter resets itself and starts Types of flip-flops:
counting again from 00, 01, 10, and 1. The count values until 1. RS Flip Flop/SR flip flop
the clock pulses are passed to J0K0 flip flop. 2. JK Flip Flop
3. D Flip Flop
4. T Flip Flop
 1. RS flip flop: This is the most common flip flop used in the digital
system. In RS flip flop, when the set input "S" is true, the output
Y will be high, and Y' will be low.

4. T Flip Flop

Just like JK flip-flop, T flip flop is used. Unlike JK flip flop, in T flip flop,
there is only single input with the clock input. The T flip flop is
constructed by connecting both of the inputs of JK flip flop together
2. J-K Flip-flop as a single input.

The JK flip flop is used to remove the drawback of the S-R flip flop, i.e.,
undefined states. The JK flip flop is formed by doing modification in
the SR flip flop. The S-R flip flop is improved in order to construct the
J-K flip flop. When S and R input is set to true, the SR flip flop gives an
inaccurate result. But in the case of JK flip flop, it gives the correct
output.

3. D Flip Flop

D flip flop is a widely used flip flop in digital systems. The D flip flop is
mostly used in shift-registers, counters, and input synchronization.
 [Link] the Common Bus Organization of a basic
computer with diagram Connections:
• The outputs of all the registers except the OUTR (output
The diagram of the common bus system is as shown below. register) are connected to the common bus.
• The output selected depends upon the binary value of
variables S2, S1 and S0.
• The lines from common bus are connected to the inputs of the
registers and memory.
• A register receives the information from the bus when its LD
(load) input is activated while in case of memory the Write
input must be enabled to receive the information.
• The contents of memory are placed onto the bus when its
Read input is activated.
• The memory receives the contents of the bus when its write
input is activated. The memory places its 16-bit output onto
the bus when the read input is activated and S2S1S0 = 111.
Various Registers:
4 registers DR, AC, IR and TR have 16 bits and 2 registers AR and PC
have 12 bits. The INPR and OUTR have 8 bits each. The INPR
receives character from input device and delivers it to the AC while
the OUTR receives character from AC and transfers it to the output
device. 5 registers have 3 control inputs LD (load), INR (increment)
and CLR (clear). These types of registers are similar to a binary
counter.

Adder and logic circuit:

The adder and logic circuit provides the 16 inputs of AC. This circuit
has 3 sets of inputs. One set comes from the outputs of AC which
implements register micro operations. The other set comes from
the DR (data register) which are used to perform arithmetic and
logic micro operations. The result of these operations is sent to AC
while the end around carry is stored in E as shown in diagram. The
third set of inputs is from INPR.
 [Link] the memory Reference inststructions The BUN instruction allows the programmer to specify an instruction
out of sequence and we say that the program branches (or jumps)
1. AND to AC: This instruction performs the AND logic operation unconditionally. The instruction is executed with one
on pairs of bits in AC and the memory word specified by the microoperation:
effective address. The result of the operation is transferred to PC ← AR
Accumulator. The microoperations that execute this instruction 5. BSA: Branch and Save Return Address
are: This instruction is useful for branching to a portion of the program
DR←M[AR] called a subroutine or procedure. When executed, the BSA
AC←AC ∧ DR, SC←0. instruction stores the address of the next instruction in sequence
(which is available in PC) into a memory location specified by the
2 .ADD: ADD to AC
effective address. The effective address plus one is then transferred
This instruction adds the content of the memory word that is
to PC to serve as the address of the first instruction in the subroutine.
denoted by the effective address to the value of AC. The rnicroopera- This operation was specified with the following register transfer:
tions needed to execute this instruction are M[AR] <-- PC, PC <-- AR + I
DR← M[AR] 5. ISZ : Increment and Skip if Zero
AC← AC + DR. ISZ instruction increments the word referred by the effective
2. LDA: Load to AC address, and if the incremented value of the word is equal to 0,
This instruction transfers the memory word specified by the effective PC is incremented by 1.
address to AC . The microoperations needed to execute this DR ←MR[AR]
instruction are DR ← DR + 1
M[AR] ←DR, if (DR = 0) then (PC ← PC +1), SC ← 0
DR← M[AR] [AR]
AC← DR
3. STA: Store AC [Link] is DMA ? Draw its Block diagram and also explain
This instruction stores the content of AC into the memory word its working
specified by the effective address. Since the output of AC is applied
Direct Memory Access (DMA):
to the bus and the data input of memory is connected to the bus, we
can execute this instruction with one micro operation The transfer of data between a fast storage device such as magnetic
M [AR] ← AC disk and memory is often limited by the speed of the CPU. Removing
the CPU from the path and letting the peripheral device manage the
4. BUN: Branch Unconditionally memory buses directly would improve the speed of transfer. This
transfer technique is called Direct Memory Access(DMA).During the
This instruction transfers the program to the instruction specified by DMA transfer, the CPU is idle and has no control of the memory buses.
the effective address.
A DMA Controller takes over the buses to manage the transfer directly
between the

I/O device and memory.

The CPU may be placed in an idle state in a variety of ways. One

common method

extensively used in microprocessor is to disable the buses through

special control

signals

such as:
The CPU activates the Bus Grant (BG) output to inform the
◼ Bus Request (BR)
external DMA that the
◼ Bus Grant (BG)
Bus Request (BR) can now take control of the buses to conduct
These two control signals in the CPU that facilitates the DMA transfer. memory transfer
The Bus
without processor. When the DMA terminates the transfer, it
Request (BR) input is used by the DMA controller to request the CPU. disables the Bus
When this input is
Request (BR) line. The CPU disables the Bus Grant (BG), takes
active, the CPU terminates the execution of the current instruction control of the buses
and places the
and return to its normal operation.
address bus, data bus and read write lines into a high Impedance
The transfer can be made in several ways that are:
state. High
Impedance state means that the output is disconnected i. DMA Burst

ii. Cycle Stealing

i) DMA Burst :- In DMA Burst transfer, a block sequence

consisting of a number of

memory words is transferred in continuous burst while the DMA

controller is
 master shifted to the left or the right.  During a shift-left operation the
serial input transfers a bit into the rightmost position.  During
of the memory buses. a shift-right operation the serial input transfers a bit into the
ii) Cycle Stealing :- Cycle stealing allows the DMA controller to leftmost position.  There are three types of shifts: logical,
transfer one data circular, and arithmetic.  The symbolic notation for the shift
word at a time, after which it must returns control of the buses microoperations is shown in Table
to the CPU.

[Link] The Logic and shift Micro Operations

Logic microoperations specify binary operations for strings of bits
stored in registers. These operations consider each bit of the register
separately and treat them as binary variables.
Following is the list of Logic Micro Operations:

Shift Microoperations:  Shift microoperations are used for

serial transfer of data.  The contents of a register can be
19