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TMP275
SBOS363F – JUNE 2006 – REVISED MAY 2018

TMP275 ±0.5°C Temperature Sensor With I2C and SMBus Interface in Industry Standard
LM75 Form Factor and Pinout
1 Features 3 Description
1• High Accuracy: The TMP275 is a ±0.5°C accurate integrated digital
temperature sensor with a 12-bit analog-to-digital
– ±0.5°C (Maximum) From −20°C to 100°C converter (ADC) that can operate as low as 2.7-V
– ±1°C (Maximum) From −40°C to 125°C supply voltage and is pin- and register-compatible
• Low Quiescent Current: with the Texas Instruments LM75, TMP75, TMP75B,
and TMP175 devices. This device is available in
– 50 μA (Typical)
SOIC-8 and VSSOP-8 packages, and it requires no
– 0.1-μA Standby external components to sense the temperature. The
• Resolution: 9 to 12 Bits, User-Selectable TMP275 is capable of reading temperatures with a
• Digital Output: SMBus™, Two-Wire, and I2C maximum resolution of 0.0625°C (12 bits) and as low
as 0.5°C (9 bits), which allows the user to maximize
Interface Compatibility
efficiency by programming for higher resolution or
• 8 I2C/SMBus Addresses faster conversion time. The device is specified over a
• Wide Supply Range: 2.7 V to 5.5 V temperature range of –40°C to 125°C.
• Small VSSOP-8 and SOIC-8 Packages The TMP275 device features SMBus and two-wire
• No Specified Power-up Sequence Required; Two- interface compatibility, and allows up to eight devices
Wire Bus Pullups May Be Enabled Before V+ on the same bus with the SMBus overtemperature
alert function. The factory-calibrated temperature
2 Applications accuracy and the noise-immune digital interface
make the TMP275 the preferred solution for
• Power-Supply Temperature Monitoring temperature compensation of other sensors and
• Computer Peripheral Thermal Protection electronic components, without the need for
• Battery Management additional system-level calibration or elaborate board
layout for distributed temperature sensing.
• Office Machines
• Servers Device Information(1)
• Thermostat Controls PART NUMBER PACKAGE BODY SIZE (NOM)
• Environmental Monitoring and HVAC SOIC (8) 4.90 mm × 3.91 mm
TMP275
• Electromechanical Device Temperature VSSOP (8) 3.00 mm × 3.00 mm

• Data Logger (1) For all available packages, see the package option addendum
at the end of the data sheet.
Simplified Schematic Internal Block Diagram
Supply Voltage
Temperature
2.7V to 5.5V

Supply Bypass Diode

Capacitor 1 Control 8
SDA Temp. V+
Pullup Resistors 0.01 µF Logic
5k
Sensor

2 7
SCL A0
ΔΣ
Serial
1
SDA
TMP275
V+
8 A/D
Interface
Two-Wire Converter
Host Controller 2 7 3 6
SCL A0 ALERT A1
3 6
ALERT A1

4 5 Config.
GND A2 4 5
GND OSC and Temp. A2
Register

An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
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Table of Contents
1 Features .................................................................. 1 7.4 Device Functional Modes........................................ 14
2 Applications ........................................................... 1 7.5 Programming .......................................................... 15
3 Description ............................................................. 1 8 Application and Implementation ........................ 19
4 Revision History..................................................... 2 8.1 Application Information............................................ 19
8.2 Typical Applications ................................................ 19
5 Pin Configuration and Functions ......................... 3
6 Specifications......................................................... 4 9 Power Supply Recommendations...................... 22
6.1 Absolute Maximum Ratings ...................................... 4 10 Layout................................................................... 22
6.2 ESD Ratings ............................................................ 4 10.1 Layout Guidelines ................................................. 22
6.3 Recommended Operating Conditions....................... 4 10.2 Layout Example .................................................... 23
6.4 Thermal Information ................................................. 4 11 Device and Documentation Support ................. 24
6.5 Electrical Characteristics........................................... 5 11.1 Documentation Support ........................................ 24
6.6 Timing Requirements ................................................ 6 11.2 Community Resources.......................................... 24
6.7 Typical Characteristics .............................................. 7 11.3 Trademarks ........................................................... 24
7 Detailed Description .............................................. 8 11.4 Electrostatic Discharge Caution ............................ 24
7.1 Overview ................................................................... 8 11.5 Glossary ................................................................ 24
7.2 Functional Block Diagram ......................................... 8 12 Mechanical, Packaging, and Orderable
7.3 Feature Description................................................... 8 Information ........................................................... 24

4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.

Changes from Revision E (November 2015) to Revision F Page

• Added repeatability parameter to the Electrical Characteristics table .................................................................................... 5

• Added long-term drift parameter to the Electrical Characteristics table ................................................................................. 5

Changes from Revision D (August 2007) to Revision E Page

• Added Handling Rating table, Feature Description section, Device Functional Modes, Application and
Implementation section, Power Supply Recommendations section, Layout section, Device and Documentation
Support section, and Mechanical, Packaging, and Orderable Information section ............................................................... 1
• Changed the Timing Requirements table with new I2C data. Updated affected values throughout the data sheet .............. 6

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5 Pin Configuration and Functions

D and DGK Packages

8-Pin SOIC and 8-Pin VSSOP
Top View

SDA 1 8 V+

SCL 2 7 A0

ALERT 3 6 A1

GND 4 5 A2

Pin Functions
PIN
I/O DESCRIPTION
NO. NAME
1 SDA I/O Serail data. Open-drain output; requires a pullup resistor.
2 SCL I Serial clock. Open-drain output; requires a pullpup resistor.
3 ALERT O Overtemperature alert. Open-drain output; requires a pullup resistor.
4 GND — Ground
5 A2 I Address select. Connect to GND or V+.
6 A1 I Address select. Connect to GND or V+.
7 A0 I Address select. Connect to GND or V+.
8 V+ I Supply voltage, 2.7 to 5.5 V

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6 Specifications
6.1 Absolute Maximum Ratings
(1)
over operating free-air temperature range (unless otherwise noted)
MIN MAX UNIT
Power supply, V+ 7 V
(2)
Input voltage –0.5 7 V
Input current 10 mA
Operating temperature –55 127 °C
Junction temperature, TJ max, 150 °C
Storage temperature, Tstg –60 130 °C

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

6.2 ESD Ratings

VALUE UNIT
Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all pins (1) ±4000
Electrostatic
V(ESD) Charged device model (CDM), per JEDEC specification JESD22-C101, all pins (2) ±1000 V
discharge
Machine Model (MM) ±300

(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

6.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)
MIN NOM MAX UNIT
Supply voltage 2.7 5.5 V
Operating free-air temperature, TA –40 125 °C

6.4 Thermal Information

TMP275
(1)
THERMAL METRIC D (SOIC) AND DGK (VSSOP) UNIT
8 PINS
RθJA Junction-to-ambient thermal resistance 120 °C/W
RθJC(top) Junction-to-case (top) thermal resistance 66.7 °C/W
RθJB Junction-to-board thermal resistance 60.4 °C/W
ψJT Junction-to-top characterization parameter 17.8 °C/W
ψJB Junction-to-board characterization parameter 59.9 °C/W
RθJC(bot) Junction-to-case (bottom) thermal resistance N/A °C/W

(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.

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6.5 Electrical Characteristics

at TA = −40°C to +125°C, and V+ = 2.7 V to 5.5 V (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
TEMPERATURE INPUT
Range –40 125 °C
–20°C to 100°C, V+ = 3.3 V ±0.0625 ±0.5 °C
0°C to 100°C, V+ = 3 V to 3.6 V ±0.0625 ±0.75 °C
Accuracy (Temperature Error)
–40°C to 125°C, V+ = 3 V to 3.6 V ±0.0625 ±1 °C
25°C to 100°C, V+ = 3.3 V to 5.5 V 0.2 ±1.5 °C
Resolution (1) Selectable 0.0625 °C
Repeatability (2) 25°C, V+= 3.3 V (3) ±0.0625 °C
(4)
Long-term drift 500 hours at 150°C ±0.0625 °C
DIGITAL INPUT/OUTPUT
Input Capacitance 3 pF
Input logic level, HIGH, VIH 0.7(V+) 6 V
Input logic level, LOW, VIL −0.5 0.3(V+) V
Leakage Input Current, IIN 0 V ≤ VIN ≤ 6 V 1 µA
Input Voltage Hysteresis SCL and SDA pins 500 mV
SDA Output logic level, LOW, VOL IOL = 3 mA 0 0.15 0.4 V
ALERT Output logic level, HIGH, VOL IOL = 4 mA 0 0.15 0.4 V
Resolution Selectable 9 to 12 Bits
9-Bit 27.5 37.5 ms
10-Bit 55 75 ms
Coversion Time
11-Bit 110 150 ms
12-Bit 220 300 ms
Time-out time 25 54 74 ms
POWER SUPPLY
Operating range 2.7 5.5 V
Serial bus inactive 50 85 µA
Quiescent Current, IQ Serial bus active, SCL freq = 400 kHz 100 µA
Serial bus active, SCL freq = 3.4 MHz 410 µA
Serial bus inactive 0.1 3 µA
Shutdown Current, ISD Serial bus active, SCL freq = 400 kHz 60 µA
Serial bus active, SCL freq = 3.4 MHz 380 µA
TEMPERATURE RANGE
Specified Range –40 125 °C
Operating Range –55 127 °C

(1) Specified for 12-bit resolution.

(2) Repeatability is the ability to reproduce a reading when the measured temperature is applied consecutively, under the same conditions.
(3) One-shot mode setup, 1 sample per minute for 24 hours.
(4) Long-term drift is determined using accelerated operational life testing at a junction temperature of 150°C.

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6.6 Timing Requirements

See the Timing Diagrams section for timing diagrams. (1)
HIGH-SPEED
FAST MODE
MODE UNIT
MIN MAX MIN MAX
ƒ(SCL) SCL operating frequency V+ 0.001 0.4 0.001 2.38 MHz
Bus-free time between STOP and START
t(BUF) 1300 160 ns
condition
Hold time after repeated START condition.
t(HDSTA) 600 160 ns
After this period, the first clock is generated.
t(SUSTA) Repeated start condition setup time See Timing Diagrams 600 160 ns
t(SUSTO) STOP condition setup time 600 160 ns
t(HDDAT) Data hold time 4 900 4 120 ns
t(SUDAT) Data setup time 100 10 ns
t(LOW) SCL-clock low period V+ , see Timing Diagrams 1300 280 ns
t(HIGH) SCL-clock high period See Timing Diagrams 600 60 ns
tFD Data fall time See Timing Diagrams 300 150 ns
See Timing Diagrams 300 40 ns
tRC Clock rise time SCLK ≤ 100 kHz, See Timing
1000 ns
Diagrams
tFC Clock fall time See Timing Diagrams 300 40 ns

(1) Values based on a statistical analysis of a one-time sample of devices. Minimum and maximum values are not specified and not
production tested.

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6.7 Typical Characteristics

at TA = 25°C and V+ = 5 V (unless otherwise noted)

85 1.0
0.9
75 0.8
0.7
65
0.6
V+ = 5 V

ISD (μA)
IQ (μA)

0.5
55
0.4
0.3
45
0.2
V+ = 2..7V
35 0.1
0.0
Serial Bus Inactive
25 −0.1
−55 −35 −15 5 25 45 65 85 105 125 130 −55 −35 −15 5 25 45 65 85 105 125 130
Temperature (°C) Te mperature (°C)

Figure 1. Quiescent Current vs Temperature Figure 2. Shutdown Current vs Temperature

300 0.500

0.375
V+ = 5 V
Tempe rature Error (°C)
Conversion Time (ms)

250 0.250

0.125

200 0
V+ = 2..7 V
−0.125

150 −0.250
−0.375
12-bit resolution
100 −0.500
−55 −35 −15 5 25 45 65 85 105 125 130 −55 −35 −15 5 25 45 65 85 105 125 130

Te mperature (°C) Temperature (° C)

Figure 3. Conversion Time vs Temperature Figure 4. Temperature Error vs Temperature

500
Hs MODE
450
FAST MODE
400
350
Population

300
IQ (μA)

250
200
125°C
150
25°C
100
50
−55°C
0
−0.50

−0.40

−0.30

−0.20

−0.10

0.00

0.10

0.20

0.30

0.40

0.50

1k 10k 100k 1M 10M

Frequency (Hz) Temperature Error (° C)

Figure 5. Quiescent Current with Bus Activity Figure 6. Temperature Error at 25°C
vs Temperature

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7 Detailed Description

7.1 Overview
The TMP275 is a digital temperature sensor that is optimal for thermal management and thermal protection
applications. The TMP275 is Two-Wire, SMBus, and I2C interface-compatible, and is specified over a
temperature range of −40°C to 125°C. The temperature sensor in the TMP275 is the chip itself. Thermal paths
run through the package leads as well as the plastic package. The package leads provide the primary thermal
path because of the lower thermal resistance of the metal. See Functional Block Diagram for the internal block
diagram of TMP275 device.

7.2 Functional Block Diagram

Temperature

Diode
1 Control 8
SDA Temp. V+
Logic
Sensor

2 7
SCL A0
ΔΣ
Serial
A/D
Interface
Converter
3 6
ALERT A1

Config.
4 5
GND OSC and Temp. A2
Register

7.3 Feature Description

7.3.1 Digital Temperature Output
The temperature register of the TMP275 is a 12-bit, read-only register that stores the output of the most recent
conversion. Two bytes must be read to obtain data, and are described in Figure 13 and Figure 14. Note that byte
1 is the most significant byte, followed by byte 2, the least significant byte. The first 12 bits are used to indicate
temperature, with all remaining bits equal to zero. The least significant byte does not have to be read if that
information is not needed. Data format for temperature is summarized in Table 1. Following power up or reset,
the Temperature Register reads 0°C until the first conversion is complete. The user can obtain 9, 10, 11, or 12
bits of resolution by addressing the Configuration Register and setting the resolution bits accordingly. For 9-, 10-,
or 11-bit resolution, the most significant bits in the Temperature Register are used with the unused LSBs set to
zero

Table 1. Temperature Data Format

TEMPERATURE DIGITAL OUTPUT
HEX
(°C) (BINARY)
128 0111 1111 1111 7FF
127.9375 0111 1111 1111 7FF
100 0110 0100 0000 640
80 0101 0000 0000 500
75 0100 1011 0000 4B0
50 0011 0010 0000 320
25 0001 1001 0000 190
0.25 0000 0000 0100 004
0 0000 0000 0000 000
–0.25 1111 1111 1100 FFC
–25 1110 0111 0000 E70
–55 1100 1001 0000 C90

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7.3.2 Serial Interface

The TMP275 operates only as slave devices on the SMBus, Two-Wire, and I2C interface-compatible bus.
Connections to the bus are made through the open-drain I/O lines SDA and SCL. The SDA and SCL pins feature
integrated spike suppression filters and Schmitt triggers to minimize the effects of input spikes and bus noise.
The TMP275 supports the transmission protocol for fast (up to 400 kHz) and high-speed (up to 2.38 MHz)
modes. All data bytes are transmitted MSB first.

7.3.3 Bus Overview

The device that initiates the transfer is called a master, and the devices controlled by the master are slaves. The
bus must be controlled by a master device that generates the serial clock (SCL), controls the bus access, and
generates the START and STOP conditions.
To address a specific device, a START condition is initiated, indicated by pulling the data-line (SDA) from a
HIGH to LOW logic level while SCL is HIGH. All slaves on the bus shift in the slave address byte, with the last bit
indicating whether a read or write operation is intended. During the ninth clock pulse, the slave being addressed
responds to the master by generating an Acknowledge and pulling SDA LOW.
Data transfer is then initiated and sent over eight clock pulses followed by an Acknowledge Bit. During data
transfer SDA must remain stable while SCL is HIGH, as any change in SDA while SCL is HIGH will be
interpreted as a control signal.
Once all data has been transferred, the master generates a STOP condition indicated by pulling SDA from LOW
to HIGH, while SCL is HIGH.

7.3.4 Serial Bus Address

To communicate with the TMP275, the master must first address slave devices through a slave address byte.
The slave address byte consists of 7 address bits, and a direction bit indicating the intent of executing a read or
write operation.
The TMP275 features three address pins, allowing up to eight devices to be connected per bus. Pin logic levels
are described in Table 2. The address pins of the TMP275 are read after reset, at start of communication, or in
response to a Two-Wire address acquire request. Following reading the state of the pins the address is latched
to minimize power dissipation associated with detection.

Table 2. Address Pins and Slave Addresses for the TMP275

A2 A1 A0 SLAVE ADDRESS
0 0 0 1001000
0 0 1 1001001
0 1 0 1001010
0 1 1 1001011
1 0 0 1001100
1 0 1 1001101
1 1 0 1001110
1 1 1 1001111

[Link] Writing and Reading to the TMP275

Accessing a particular register on the TMP275 is accomplished by writing the appropriate value to the Pointer
Register. The value for the Pointer Register is the first byte transferred after the slave address byte with the R/W
bit LOW. Every write operation to the TMP275 requires a value for the Pointer Register (see Figure 8).

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When reading from the TMP275, the last value stored in the Pointer Register by a write operation is used to
determine which register is read by a read operation. To change the register pointer for a read operation, a new
value must be written to the Pointer Register. This is accomplished by issuing a slave address byte with the R/W
bit LOW, followed by the Pointer Register Byte. No additional data is required. The master can then generate a
START condition and send the slave address byte with the R/W bit HIGH to initiate the read command. See
Figure 9 for details of this sequence. If repeated reads from the same register are desired, it is not necessary to
continually send the Pointer Register bytes, as the TMP275 remembers the Pointer Register value until it is
changed by the next write operation.
Note that register bytes are sent most-significant byte first, followed by the least significant byte.

[Link] Slave Mode Operations

The TMP275 can operate as a slave receiver or slave transmitter.

[Link].1 Slave Receiver Mode

The first byte transmitted by the master is the slave address, with the R/W bit LOW. The TMP275 then
acknowledges reception of a valid address. The next byte transmitted by the master is the Pointer Register. The
TMP275 then acknowledges reception of the Pointer Register byte. The next byte or bytes are written to the
register addressed by the Pointer Register. The TMP275 acknowledges reception of each data byte. The master
may terminate data transfer by generating a START or STOP condition.

[Link].2 Slave Transmitter Mode

The first byte is transmitted by the master and is the slave address, with the R/W bit HIGH. The slave
acknowledges reception of a valid slave address. The next byte is transmitted by the slave and is the most
significant byte of the register indicated by the Pointer Register. The master acknowledges reception of the data
byte. The next byte transmitted by the slave is the least significant byte. The master acknowledges reception of
the data byte. The master may terminate data transfer by generating a Not-Acknowledge on reception of any
data byte, or generating a START or STOP condition.

[Link] SMBus Alert Function

The TMP275 supports the SMBus Alert function. When the TMP275 is operating in Interrupt Mode (TM = 1), the
ALERT pin of the TMP275 may be connected as an SMBus Alert signal. When a master senses that an ALERT
condition is present on the ALERT line, the master sends an SMBus Alert command (00011001) on the bus. If
the ALERT pin of the TMP275 is active, the device acknowledges the SMBus Alert command and responds by
returning its slave address on the SDA line. The eighth bit (LSB) of the slave address byte indicates if the
temperature exceeding THIGH or falling below TLOW caused the ALERT condition. This bit will be HIGH if the
temperature is greater than or equal to THIGH. This bit will be LOW if the temperature is less than TLOW. Refer to
Figure 10 for details of this sequence.
If multiple devices on the bus respond to the SMBus Alert command, arbitration during the slave address portion
of the SMBus Alert command determines which device clears its ALERT status. If the TMP275 wins the
arbitration, its ALERT pin becomes inactive at the completion of the SMBus Alert command. If the TMP275 loses
the arbitration, its ALERT pin remains active.

[Link] General Call

The TMP275 responds to a Two-Wire General Call address (0000000) if the eighth bit is 0. The device
acknowledges the General Call address and responds to commands in the second byte. If the second byte is
00000100, the TMP275 latches the status of their address pins, but will not reset. If the second byte is
00000110, the TMP275 latches the status of their address pins and reset their internal registers to their power-up
values.

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[Link] High-Speed Mode

For the Two-Wire bus to operate at frequencies above 400 kHz, the master device must issue an Hs-mode
master code (00001XXX) as the first byte after a START condition to switch the bus to high-speed operation.
The TMP1275 device will not acknowledge this byte, but will switch their input filters on SDA and SCL and their
output filters on SDA to operate in Hs-mode, allowing transfers at up to 2.38 MHz. After the Hs-mode master
code has been issued, the master will transmit a Two-Wire slave address to initiate a data transfer operation.
The bus will continue to operate in Hs-mode until a STOP condition occurs on the bus. Upon receiving the STOP
condition, the TMP275 switches the input and output filter back to fast-mode operation.

[Link] Time-Out Function

The TMP275 resets the serial interface if either SCL or SDA is held LOW for 54 ms (typical) between a START
and STOP condition. The TMP275 releases the bus if it is pulled LOW and waits for a START condition. To
avoid activating the time-out function, it is necessary to maintain a communication speed of at least 1 kHz for
SCL operating frequency.

7.3.5 Timing Diagrams

The TMP275 is Two-Wire, SMBUs, and I2C interface-compatible. Figure 7 to Figure 10 describe the various
operations on the TMP275. Bus definitions are given below. Parameters for Figure 7 are defined in Timing
Requirements.
Bus Idle: Both SDA and SCL lines remain HIGH.
Start Data Transfer: A change in the state of the SDA line, from HIGH to LOW, while the SCL line is HIGH,
defines a START condition. Each data transfer is initiated with a START condition.
Stop Data Transfer: A change in the state of the SDA line from LOW to HIGH while the SCL line is HIGH
defines a STOP condition. Each data transfer is terminated with a repeated START or STOP condition.
Data Transfer: The number of data bytes transferred between a START and a STOP condition is not limited and
is determined by the master device. The receiver acknowledges the transfer of data.
Acknowledge: Each receiving device, when addressed, is obliged to generate an Acknowledge bit. A device
that acknowledges must pull down the SDA line during the Acknowledge clock pulse in such a way that the SDA
line is stable LOW during the HIGH period of the Acknowledge clock pulse. Setup and hold times must be taken
into account. On a master receive, the termination of the data transfer can be signaled by the master generating
a Not-Acknowledge on the last byte that has been transmitted by the slave.

7.3.6 Two-Wire Timing Diagrams

t(LOW)
tR tF t(HDSTA)

SCL

t(HDSTA) t(HIGH) t(SUSTA) t(SUSTO)

t(HDDAT) t(SUDAT)

SDA
t(BUF)

P S S P

Figure 7. Two-Wire Timing Diagram

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1 9 1 9

SCL …

SDA 1 0 0 1 A2 A1 A0 R/W 0 0 0 0 0 0 P1 P0 …
Start By ACK By ACK By
Master TMP275 TMP275
Frame 1Two–Wire Slave Address Byte Frame 2 Pointer Register Byte

1 9 1 9
SCL
(Continued)

SDA
D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0
(Continued)
ACK By ACK By Stop By
TMP275 TMP275 Master
Frame 3 Data Byte 1 Frame 4 Data Byte 2

Figure 8. Two-Wire Timing Diagram for TMP275 Write Word Format

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1 9 1 9

SCL …

SDA 1 0 0 1 0 0 0 R/W 0 0 0 0 0 0 P1 P0 …
Start By ACK By ACK By
Master TMP275 TMP275

Frame 1 Two–Wire Slave Address Byte Frame 2 Pointer Register Byte

1 9 1 9
SCL …
(Continued)

SDA
1 0 0 1 0 0 0 R/W D7 D6 D5 D4 D3 D2 D1 D0 …
(Continued)
Start By ACK By From ACK By
Master TMP275 TMP275 Master
Frame 3 Two–Wire Slave Address Byte Frame 4 Data Byte 1 Read Register

1 9
SCL
(Continued)

SDA
D7 D6 D5 D4 D3 D2 D1 D0
(Continued)
From ACK By Stop By
TMP275 Master Master
Frame 5 Data Byte 2 Read Register NOTE: Address Pins A0, A1, A2 = 0

Figure 9. Two-Wire Timing Diagram for Read Word Format

ALERT

1 9 1 9

SCL

SDA 0 0 0 1 1 0 0 R/W 1 0 0 1 0 0 0 S ta t u s

Start By ACK By From NACK By Stop By

Master TMP275 TMP275 Master Master

Frame 1 SMBus ALERT Response Address Byte

NOTE: Address Pins A0, A1, A2 =0

Figure 10. Timing Diagram for SMBus ALERT

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7.4 Device Functional Modes

7.4.1 Shutdown Mode (SD)
The Shutdown Mode of the TMP275 allows the user to save maximum power by shutting down all device
circuitry other than the serial interface, which reduces current consumption to typically less than 0.1 μA.
Shutdown Mode is enabled when the SD bit is 1; the device will shut down once the current conversion is
completed. When SD is equal to 0, the device maintains a continuous conversion state.

7.4.2 Thermostat Mode (TM)

The Thermostat Mode bit of the TMP275 indicates to the device whether to operate in Comparator Mode (TM =
0) or Interrupt Mode (TM = 1). For more information on comparator and interrupt modes, see the High and Low
Limit Registers section.

[Link] Comparator Mode (TM = 0)

In Comparator mode (TM = 0), the ALERT pin is activated when the temperature equals or exceeds the value in
the T(HIGH) register and it remains active until the temperature falls below the value in the T(LOW) register. For
more information on the comparator mode, see the High and Low Limit Registers section.

[Link] Interrupt Mode (TM = 1)

In Interrupt mode (TM = 1), the ALERT pin is activated when the temperature exceeds T(HIGH) or goes below
T(LOW) registers. The ALERT pin is cleared when the host controller reads the temperature register. For more
information on the interrupt mode, see the High and Low Limit Registers section.

7.4.3 One-Shot (OS)

The TMP275 features a One-Shot Temperature Measurement Mode. When the device is in Shutdown Mode,
writing a ‘1’ to the OS bit starts a single temperature conversion. The device returns to the shutdown state at the
completion of the single conversion. This mode is useful for reducing power consumption in the TMP275 when
continuous temperature monitoring is not required. When the configuration register is read, the OS always reads
zero.

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7.5 Programming
7.5.1 Pointer Register
Figure 11 shows the internal register structure of the TMP275. The 8-bit Pointer Register of the devices is used
to address a given data register. The Pointer Register uses the two LSBs to identify which of the data registers
should respond to a read or write command. Figure 12 identifies the bits of the Pointer Register byte. Table 3
describes the pointer address of the registers available in the TMP275. Power-up reset value of P1/P0 is 00.

Pointer
Register

Temperature
Register

SCL
Configuration
Register
I/O
Control
Interface
TLOW
Register
SDA

THIGH
Register

Figure 11. Internal Register Structure of the TMP275

[Link] Pointer Register Byte (offset = N/A) [reset = 00h]

Figure 12. Pointer Register Byte
P7 P6 P5 P4 P3 P2 P1 P0
0 0 0 0 0 0 Register Bits

[Link] Pointer Addresses of the TMP275

Table 3. Pointer Addresses of the TMP275 Field Description

P1 P0 TYPE REGISTER
0 0 R only, default Temperature Register
0 1 R/W Configuration Register
1 0 R/W TLOW Register
1 1 R/W THIGH Register

7.5.2 Temperature Register

The Temperature Register of the TMP275 is a 12-bit, read-only register that stores the output of the most recent
conversion. Two bytes must be read to obtain data, and are described in Figure 13 and Figure 14. Note that byte
1 is the most significant byte, followed by byte 2, the least significant byte. The first 12 bits are used to indicate
temperature, with all remaining bits equal to zero. The least significant byte does not have to be read if that
information is not needed. Data format for temperature is summarized in Table 1. Following power up or reset,
the Temperature Register reads 0°C until the first conversion is complete.

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Figure 13. Byte 1 of Temperature Register

D7 D6 D5 D4 D3 D2 D1 D0
T11 T10 T9 T8 T7 T6 T5 T4

Figure 14. Byte 2 of Temperature Register

D7 D6 D5 D4 D3 D2 D1 D0
T3 T2 T1 T0 0 0 0 0

7.5.3 Configuration Register

The Configuration Register is an 8-bit read/write register used to store bits that control the operational modes of
the temperature sensor. Read/write operations are performed MSB first. The format of the Configuration Register
for the TMP275 is shown in Table 4, followed by a breakdown of the register bits. The power-up/reset value of
the Configuration Register is all bits equal to 0.

Table 4. Configuration Register Format

BYTE D7 D6 D5 D4 D3 D2 D1 D0
1 OS R1 R0 F1 F0 POL TM SD

7.5.4 Shutdown Mode (SD)

The Shutdown Mode of the TMP275 allows the user to save maximum power by shutting down all device
circuitry other than the serial interface, which reduces current consumption to typically less than 0.1 μA.
Shutdown Mode is enabled when the SD bit is 1; the device shuts down once the current conversion is
completed. When SD is equal to 0, the device maintains a continuous conversion state.

7.5.5 Thermostat Mode (TM)

The Thermostat Mode bit of the TMP275 indicates to the device whether to operate in Comparator Mode (TM =
0) or Interrupt Mode (TM = 1). For more information on Comparator and Interrupt modes, see the High and Low
Limit Registers section.

7.5.6 Polarity (POL)

The Polarity Bit of the TMP275 allows the user to adjust the polarity of the ALERT pin output. If POL = 0, the
ALERT pin is active LOW, as shown in Figure 15. For POL = 1, the ALERT pin is active HIGH, and the state of
the ALERT pin is inverted.

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T HIG H
Measured
Temperature

TL O W

TMP275 ALER T PIN

(Comparator Mode)
POL =0

TMP275 ALER T PIN

(Interrupt Mode)
POL =0

TMP275 ALER T PIN

(Comparator Mode)
POL =1
TMP275 ALER T PIN
(Interrupt Mode)
POL =1

Read Read Read

Time

Figure 15. Output Transfer Function Diagrams

7.5.7 Fault Queue (F1/F0)

A fault condition is defined as when the measured temperature exceeds the user-defined limits set in the THIGH
and TLOW Registers. Additionally, the number of fault conditions required to generate an alert may be
programmed using the fault queue. The fault queue is provided to prevent a false alert as a result of
environmental noise. The fault queue requires consecutive fault measurements to trigger the alert function.
Table 5 defines the number of measured faults that may be programmed to trigger an alert condition in the
device. For THIGH and TLOW register format and byte order, see the section High and Low Limit Registers.

Table 5. Fault Settings

F1 F0 CONSECUTIVE FAULTS
0 0 1
0 1 2
1 0 4
1 1 6

7.5.8 Converter Resolution (R1/R0)

The converter resolution bits control the resolution of the internal analog-to-digital (A/D) converter. This control
allows the user to maximize efficiency by programming for higher resolution or faster conversion time. Table 6
identifies the Resolution Bits and the relationship between resolution and conversion time.

Table 6. Resolution of the TMP275

CONVERSION TIME
R1 R0 RESOLUTION
(typical)
0 0 9 Bits (0.5°C) 27.5ms
0 1 10 Bits (0.25°C) 55ms
1 0 11 Bits (0.125°C) 110ms
1 1 12 Bits (0.0625°C) 220ms

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7.5.9 One-Shot (OS)

The TMP275 features a One-Shot Temperature Measurement Mode. When the device is in Shutdown Mode,
writing a ‘1’ to the OS bit starts a single temperature conversion. The device returns to the shutdown state at the
completion of the single conversion. This mode is useful for reducing power consumption in the TMP275 when
continuous temperature monitoring is not required. When the configuration register is read, the OS always reads
zero.

7.5.10 High and Low Limit Registers

In Comparator Mode (TM = 0), the ALERT pin of the TMP275 becomes active when the temperature equals or
exceeds the value in THIGH and generates a consecutive number of faults according to fault bits F1 and F0. The
ALERT pin remains active until the temperature falls below the indicated TLOW value for the same number of
faults.
In Interrupt Mode (TM = 1), the ALERT pin becomes active when the temperature equals or exceeds THIGH for a
consecutive number of fault conditions. The ALERT pin remains active until a read operation of any register
occurs, or the device successfully responds to the SMBus Alert Response Address. The ALERT pin is also
cleared if the device is placed in Shutdown Mode. Once the ALERT pin is cleared, it only becomes active again
by the temperature falling below TLOW. When the temperature falls below TLOW, the ALERT pin becomes active
and remain active until cleared by a read operation of any register or a successful response to the SMBus Alert
Response Address. Once the ALERT pin is cleared, the above cycle repeats, with the ALERT pin becoming
active when the temperature equals or exceeds THIGH. The ALERT pin can also be cleared by resetting the
device with the General Call Reset command. This command also clears the state of the internal registers in the
device, returning the device to Comparator Mode (TM = 0).
Both operational modes are represented in Figure 15. Table 7, Table 8, Table 9, and Table 10 describe the
format for the THIGH and TLOW registers. Note that the most significant byte is sent first, followed by the least
significant byte. Power-up reset values for THIGH and TLOW are:
THIGH = 80°C and TLOW = 75°C
The format of the data for THIGH and TLOW is the same as for the Temperature Register.

Table 7. Byte 1 THIGH Register

BYTE D7 D6 D5 D4 D3 D2 D1 D0
1 H11 H10 H9 H8 H7 H6 H5 H4

Table 8. Byte 2 of THIGH Register

BYTE D7 D6 D5 D4 D3 D2 D1 D0
2 H3 H2 H1 H0 0 0 0 0

Table 9. Byte 1 TLOW Register

BYTE D7 D6 D5 D4 D3 D2 D1 D0
1 L11 L10 L9 L8 L7 L6 L5 L4

Table 10. Byte 2 of TLOW Register

BYTE D7 D6 D5 D4 D3 D2 D1 D0
2 L3 L2 L1 L0 0 0 0 0

All 12 bits for the Temperature, THIGH, and TLOW registers are used in the comparisons for the ALERT function for
all converter resolutions. The three LSBs in THIGH and TLOW can affect the ALERT output even if the converter is
configured for 9-bit resolution.

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8 Application and Implementation

NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.

8.1 Application Information

The TMP275 is digital output temperature sensor with SMBus, Two-Wire, and I2C compatible interfaces. This
device features three address pins (A0, A1, A2) allowing up to eight devices to be connected per bus. The
TMP275 require no external components for operation except for pullup resistors on SCL, SDA, and ALERT,
although TI recommends a 0.1-μF bypass capacitor. The TMP275 measures the PCB temperature of the location
it is mounted. The sensing device of the device is the chip itself. Thermal paths run through the package leads
as well as the plastic package. The lower thermal resistance of metal causes the leads to provide the primary
thermal path.

8.2 Typical Applications

8.2.1 Typical Connections of the TMP275
Supply Voltage
2.7V to 5.5V

Supply Bypass
Capacitor
Pullup Resistors 0.01 µF
5k

1 TMP275 8
SDA V+
Two-Wire
Host Controller 2 7
SCL A0

3 6
ALERT A1

4 5
GND A2

Figure 16. Typical Connections of the TMP275 Schematic

[Link] Design Requirements

Figure 16 shows TMP275 typical connections. The TMP275 device requires pullup resistors on the SCL, SDA,
and ALERT pins. The recommended value for the pullup resistor is 5 kΩ. In some applications the pullup resistor
can be lower or higher than 5 kΩ but must not exceed 3 mA of current on SCL and SDA pins, must not exceed 4
mA on ALERT pin. If the resistors are missing, the SCL and SDA lines will always be low (nearly 0 V) and the
I2C bus will not work. TI recommends a 0.1-μF bypass capacitor, as shown in Figure 16. The SCL, SDA, and
ALERT lines can be pulled up to a supply that is equal to or higher than V+ through the pullup resistors.
The ALERT pin can be configured to respond to one of the two alert functions available, Comparator Mode and
Interrupt Mode. To configure one of eight different addresses on the bus, connect A0, A1, and A2 to either a
GND pin or V+ pin. In the circuit shown in Figure 16 the comparator mode is selected and the address pins (A0,
A1, A2) are connected to ground.

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Typical Applications (continued)

[Link] Detailed Design Procedure
The TMP275 device should be placed in close proximity to the heat source that must be monitored, with a proper
layout for good thermal coupling. This placement ensures that temperature changes are captured within the
shortest possible time interval. To maintain accuracy in applications that require air or surface temperature
measurement, take care to isolate the package and leads from ambient air temperature. A thermally conductive
adhesive is helpful in achieving accurate surface temperature measurement.

[Link] Application Curve

Figure 17 shows the step response of the TMP275 device to a submersion in an oil bath of 100ºC from room
temperature (27ºC). The time-constant, or the time for the output to reach 63% of the input step, is 1.5 s. The
time-constant result depends on the printed-circuit board (PCB) that the TMP275 devices are mounted. For this
test, the TMP275 device was soldered to a two-layer PCB that measured 0.375 inches × 0.437 inches.
100
95
90
85
80
Temperature (qC)

75
70
65
60
55
50
45
40
35
30
25
-1 1 3 5 7 9 11 13 15 17 19
Time (s)

Figure 17. Temperature Step Response

8.2.2 Connecting Multiple Devices on a Single Bus

The TMP275 features three address pins allowing up to eight devices to be connected per bus. When the
TMP275 is operating in Interrupt mode (TM = 1) , the ALERT pin of the TMP275 may be connected as an
SMBus Alert signal. Figure 18 shows eight TMP275 devices connected to a MCU (master) using one single bus.
Each device that exists as a slave on the SMBus has one unique seven bit address, see Table 2 for TMP275
address options. When a master senses that an ALERT condition is present on the ALERT line, the master
sends an SMBus Alert command (00011001) on the bus. If the ALERT pin of the TMP275 is active, the device
acknowledges the SMBus Alert command and responds by returning its slave address on the SDA line. The
eighth bit (LSB) of the slave address byte indicates if the temperature exceeding THIGH or falling below TLOW
caused the ALERT condition. This bit will be HIGH if the temperature is greater than or equal to THIGH. This bit
will be LOW if the temperature is less than TLOW.
This application have eight devices connected to the bus. If multiple devices on the bus respond to the SMBus
Alert command, arbitration during the slave address portion of the SMBus Alert command determines which
device clears its ALERT status. If the TMP275 wins the arbitration, its ALERT pin becomes inactive at the
completion of the SMBus Alert command. If the TMP275 loses the arbitration, its ALERT pin remains active.

NOTE
Make sure you configure the device to operate in Interrupt Mode to enable the SMBus
feature.

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Typical Applications (continued)

Supply Voltage
2.7 V to 5.5 V

5k
0.01 µF

V+
SDA

SCL

ALERT

1 SDA TMP275 V+
8 1 SDA TMP275 8 1 SDA TMP275 8 1 SDA TMP275 8
V+ V+ V+
MCU 2 SCL 2 SCL 2 SCL 2 SCL
A0 7 A0 7 A0 7 A0 7
1 2 3 4
3 ALERT A1
6 3 ALERT 6 3 ALERT 6 3 ALERT 6
A1 A1 A1
4 GND A2 5 4 GND A2 5 4 GND A2 5 4 GND A2 5

Slave Address Slave Address Slave Address Slave Address

1001000 1001001 1001010 1001011

V+
SDA

SCL

ALERT

1 SDA TMP275 V+
8 1 SDA TMP275 8 1 SDA TMP275 8 1 SDA TMP275 8
V+ V+ V+
2 SCL 2 SCL 2 SCL 2 SCL
A0 7 A0 7 A0 7 A0 7
3 ALERT 5 6 3 ALERT 6 6 3 ALERT 7 6 3 ALERT 8 6
A1 A1 A1 A1
4 GND A2 5 4 GND A2 5 4 GND A2 5 4 GND A2 5

Slave Address Slave Address Slave Address Slave Address

1001100 1001101 1001110 1001111

Figure 18. Connecting Multiple Devices on a Single Bus

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Typical Applications (continued)

8.2.3 Temperature Data Logger for Cold Chain Management Applications
Cold chain management includes all of the means used to ensure a constant temperature for a product that is
not heat stable from the time it is manufactured or farmed until the time it is used. This includes industries such
as food, retail, medical, and pharmaceutical. Figure 19 implements a cold chain monitoring system that
measures temperature, then logs the sensor data to nonvolatile (FRAM) memory in the MCU. Figure 19 uses a
Near Field Communication (NFC) interface for wireless communication and is powered from a CR2032 coin cell
battery with a focus on low power to maximize the battery lifetime.
The microcontroller communicates with all of the sensor devices through an I2C-compatible interface. The MCU
also communicates with the NFC transponder through this interface. An NFC enabled smartphone can be used
to send configuration to the application board. For a detailed design procedure and requirements of this
application, see Ultralow Power Multi-Sensor Data Logger with NFC Interface Reference Design (TIDU821).

Coin Cell Battery

(CR2032)
3.0 Volts

5k 5k 5k

1 TMP275 8
Dynamic NFC MCU DATA
SDA V+
2
NFC
Enabled Transponder IC (MSP430FR5969) 2 7
SCL A0
Smartphone
(RF430CL331H) FRAM CLOCK 0.01 µF
3 6
ALERT A1
4 5
GND A2

Figure 19. Temperature Data Logger

9 Power Supply Recommendations

The TMP275 device operates with power supply in the range of 2.7 V to 5.5 V. A power-supply bypass capacitor
is required for stability. Place this capacitor as close as possible to the supply and ground pins of the device. A
typical value for this supply bypass capacitor is 0.01 μF. Applications with noisy or high impedance power
supplies may require additional decoupling capacitors to reject power-supply noise.

10 Layout

10.1 Layout Guidelines

Mount the TMP275 to a PCB as shown in Figure 20. For this example the A0, A1, and A2 address pins are
connected directly to ground. Connecting these pins to ground configures the device for slave address
1001000b.
• Bypass the VS pin to ground with a low-ESR ceramic bypass-capacitor. The typical recommended bypass
capacitance is a 0.1-μF ceramic capacitor with a X5R or X7R dielectric. The optimum placement is closest to
the VS and GND pins of the device. Take care in minimizing the loop area formed by the bypass-capacitor
connection, the VS pin, and the GND pin of the IC. Additional bypass capacitance can be added to
compensate for noisy or high-impedance power supplies.
• Pull up the open-drain output pins SDA , SCL and ALERT through 5-kΩ pullup resistors.

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10.2 Layout Example

Via to Power or Ground Plane

Via to Internal Layer

Pull-Up Resistors
Supply Bypass
Capacitor

Supply Voltage
SDA VS

SCL A0

ALERT A1

GND A2

Ground Plane for

Thermal Coupling
to Heat Source

Serial Bus Traces

Heat Source

Figure 20. TMP275 Layout Example

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11 Device and Documentation Support

11.1 Documentation Support

11.1.1 Related Documentation
For related documentation see the following:
• Ultralow Power Multi-sensor Data Logger with NFC Interface Reference Design (TIDU821)
• Understanding the I2C Bus (SLVA704)

11.2 Community Resources

The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At [Link], you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.

11.3 Trademarks
E2E is a trademark of Texas Instruments.
SMBus is a trademark of Intel Corporation.
All other trademarks are the property of their respective owners.
11.4 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.

11.5 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.

12 Mechanical, Packaging, and Orderable Information

The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.

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 PACKAGE OPTION ADDENDUM

[Link] 10-Nov-2025

PACKAGING INFORMATION

Orderable part number Status Material type Package | Pins Package qty | Carrier RoHS Lead finish/ MSL rating/ Op temp (°C) Part marking
(1) (2) (3) Ball material Peak reflow (6)
(4) (5)

TMP275AID Obsolete Production SOIC (D) | 8 - - Call TI Call TI -40 to 125 TMP275
TMP275AIDGKR Active Production VSSOP (DGK) | 8 2500 | LARGE T&R Yes NIPDAU | NIPDAUAG Level-2-260C-1 YEAR -40 to 125 T275
TMP275AIDGKR.B Active Production VSSOP (DGK) | 8 2500 | LARGE T&R Yes NIPDAU Level-2-260C-1 YEAR -40 to 125 T275
TMP275AIDR Active Production SOIC (D) | 8 2500 | LARGE T&R Yes NIPDAU Level-1-260C-UNLIM -40 to 125 TMP275
TMP275AIDR.B Active Production SOIC (D) | 8 2500 | LARGE T&R Yes NIPDAU Level-1-260C-UNLIM -40 to 125 TMP275
TMP275AIDR1G4 Active Production SOIC (D) | 8 2500 | LARGE T&R Yes NIPDAU Level-1-260C-UNLIM -40 to 125 TMP275
TMP275AIDR1G4.B Active Production SOIC (D) | 8 2500 | LARGE T&R Yes NIPDAU Level-1-260C-UNLIM -40 to 125 TMP275

(1)
Status: For more details on status, see our product life cycle.

(2)
Material type: When designated, preproduction parts are prototypes/experimental devices, and are not yet approved or released for full production. Testing and final process, including without limitation quality assurance,
reliability performance testing, and/or process qualification, may not yet be complete, and this item is subject to further changes or possible discontinuation. If available for ordering, purchases will be subject to an additional
waiver at checkout, and are intended for early internal evaluation purposes only. These items are sold without warranties of any kind.

(3)
RoHS values: Yes, No, RoHS Exempt. See the TI RoHS Statement for additional information and value definition.

(4)
Lead finish/Ball material: Parts may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two lines if the finish value exceeds the maximum
column width.

(5)
MSL rating/Peak reflow: The moisture sensitivity level ratings and peak solder (reflow) temperatures. In the event that a part has multiple moisture sensitivity ratings, only the lowest level per JEDEC standards is shown.
Refer to the shipping label for the actual reflow temperature that will be used to mount the part to the printed circuit board.

(6)
Part marking: There may be an additional marking, which relates to the logo, the lot trace code information, or the environmental category of the part.

Multiple part markings will be inside parentheses. Only one part marking contained in parentheses and separated by a "~" will appear on a part. If a line is indented then it is a continuation of the previous line and the two
combined represent the entire part marking for that device.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and
makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative
and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers
and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

Addendum-Page 1
 PACKAGE OPTION ADDENDUM

[Link] 10-Nov-2025

OTHER QUALIFIED VERSIONS OF TMP275 :

• Automotive : TMP275-Q1

NOTE: Qualified Version Definitions:

• Automotive - Q100 devices qualified for high-reliability automotive applications targeting zero defects

Addendum-Page 2
 PACKAGE MATERIALS INFORMATION

[Link] 24-Jul-2025

TAPE AND REEL INFORMATION

REEL DIMENSIONS TAPE DIMENSIONS

K0 P1

B0 W
Reel
Diameter
Cavity A0
A0 Dimension designed to accommodate the component width
B0 Dimension designed to accommodate the component length
K0 Dimension designed to accommodate the component thickness
W Overall width of the carrier tape
P1 Pitch between successive cavity centers

Reel Width (W1)

QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE

Sprocket Holes

Q1 Q2 Q1 Q2

Q3 Q4 Q3 Q4 User Direction of Feed

Pocket Quadrants

*All dimensions are nominal

Device Package Package Pins SPQ Reel Reel A0 B0 K0 P1 W Pin1
Type Drawing Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
TMP275AIDGKR VSSOP DGK 8 2500 330.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1
TMP275AIDGKR VSSOP DGK 8 2500 330.0 12.4 5.3 3.3 1.3 8.0 12.0 Q1
TMP275AIDR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1
TMP275AIDR1G4 SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1

Pack Materials-Page 1
 PACKAGE MATERIALS INFORMATION

[Link] 24-Jul-2025

TAPE AND REEL BOX DIMENSIONS

Width (mm)
H
W

*All dimensions are nominal

Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
TMP275AIDGKR VSSOP DGK 8 2500 366.0 364.0 50.0
TMP275AIDGKR VSSOP DGK 8 2500 367.0 367.0 38.0
TMP275AIDR SOIC D 8 2500 353.0 353.0 32.0
TMP275AIDR1G4 SOIC D 8 2500 353.0 353.0 32.0

Pack Materials-Page 2
 PACKAGE OUTLINE
DGK0008A SCALE 4.000
VSSOP - 1.1 mm max height
SMALL OUTLINE PACKAGE

C
5.05
TYP
A 4.75
0.1 C
PIN 1 INDEX AREA
SEATING
PLANE
6X 0.65
8
1

2X
3.1
1.95
2.9
NOTE 3

4
5 0.38
8X
0.25
3.1 0.13 C A B
B
2.9
NOTE 4

0.23
0.13

SEE DETAIL A
0.25
GAGE PLANE

1.1 MAX

0.7 0.15
0 -8 0.4 0.05
DETAIL A
A 20

TYPICAL

4214862/A 04/2023
PowerPAD is a trademark of Texas Instruments.
NOTES:

1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm per side.
4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm per side.
5. Reference JEDEC registration MO-187.

[Link]
 EXAMPLE BOARD LAYOUT
TM
DGK0008A VSSOP - 1.1 mm max height
SMALL OUTLINE PACKAGE

SYMM
8X (1.4) (R0.05) TYP

8X (0.45) 1 8

SYMM

6X (0.65)
5
4

SEE DETAILS

(4.4)

LAND PATTERN EXAMPLE

EXPOSED METAL SHOWN
SCALE: 15X

SOLDER MASK METAL UNDER SOLDER MASK

METAL
OPENING SOLDER MASK OPENING

EXPOSED METAL EXPOSED METAL

0.05 MAX 0.05 MIN

ALL AROUND ALL AROUND

NON-SOLDER MASK SOLDER MASK

DEFINED DEFINED
(PREFERRED)
SOLDER MASK DETAILS
15.000

4214862/A 04/2023
NOTES: (continued)

6. Publication IPC-7351 may have alternate designs.

7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
8. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown
on this view. It is recommended that vias under paste be filled, plugged or tented.
9. Size of metal pad may vary due to creepage requirement.

[Link]
 EXAMPLE STENCIL DESIGN
TM
DGK0008A VSSOP - 1.1 mm max height
SMALL OUTLINE PACKAGE

SYMM

8X (1.4) (R0.05) TYP

8X (0.45) 1 8

SYMM

6X (0.65)
5
4

(4.4)

SOLDER PASTE EXAMPLE

SCALE: 15X

4214862/A 04/2023
NOTES: (continued)

11. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
12. Board assembly site may have different recommendations for stencil design.

[Link]
 PACKAGE OUTLINE
D0008A SCALE 2.800
SOIC - 1.75 mm max height
SMALL OUTLINE INTEGRATED CIRCUIT

SEATING PLANE
.228-.244 TYP
[5.80-6.19]
.004 [0.1] C
A PIN 1 ID AREA
6X .050
[1.27]
8
1

.189-.197 2X
[4.81-5.00] .150
NOTE 3 [3.81]

4X (0 -15 )

4
5
8X .012-.020
B .150-.157 [0.31-0.51]
.069 MAX
[3.81-3.98] .010 [0.25] C A B [1.75]
NOTE 4

.005-.010 TYP
[0.13-0.25]

4X (0 -15 )

SEE DETAIL A
.010
[0.25]

.004-.010
0 -8 [0.11-0.25]
.016-.050
[0.41-1.27] DETAIL A
(.041) TYPICAL
[1.04]

4214825/C 02/2019

NOTES:

1. Linear dimensions are in inches [millimeters]. Dimensions in parenthesis are for reference only. Controlling dimensions are in inches.
Dimensioning and tolerancing per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed .006 [0.15] per side.
4. This dimension does not include interlead flash.
5. Reference JEDEC registration MS-012, variation AA.

[Link]
 EXAMPLE BOARD LAYOUT
D0008A SOIC - 1.75 mm max height
SMALL OUTLINE INTEGRATED CIRCUIT

8X (.061 )
[1.55]
SYMM SEE
DETAILS
1
8

8X (.024)
[0.6] SYMM

(R.002 ) TYP
[0.05]
5
4
6X (.050 )
[1.27]
(.213)
[5.4]

LAND PATTERN EXAMPLE

EXPOSED METAL SHOWN
SCALE:8X

SOLDER MASK SOLDER MASK

METAL METAL UNDER
OPENING OPENING SOLDER MASK

EXPOSED
METAL EXPOSED
METAL
.0028 MAX .0028 MIN
[0.07] [0.07]
ALL AROUND ALL AROUND

NON SOLDER MASK SOLDER MASK

DEFINED DEFINED

SOLDER MASK DETAILS

4214825/C 02/2019

NOTES: (continued)

6. Publication IPC-7351 may have alternate designs.

7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.

[Link]
 EXAMPLE STENCIL DESIGN
D0008A SOIC - 1.75 mm max height
SMALL OUTLINE INTEGRATED CIRCUIT

8X (.061 )
[1.55] SYMM

1
8

8X (.024)
[0.6] SYMM

(R.002 ) TYP
5 [0.05]
4
6X (.050 )
[1.27]
(.213)
[5.4]

SOLDER PASTE EXAMPLE

BASED ON .005 INCH [0.125 MM] THICK STENCIL
SCALE:8X

4214825/C 02/2019

NOTES: (continued)

8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.

[Link]
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