LECT1: Signal description if 8086:

three groups:
1. signals having common functions in minimum as well as
maximum mode,
2. signals have special functions for minimum mode
3. signals having special functions for maximum mode.
1.2 PHYSICAL MEMORY ORGANISATION:

• 1Mbytes memory
• organized as odd bank and even bank, each of 5l2 Kbytes,
addressed in parallel by the processor
• Byte data with even address is transferred on D7-D0, while the
byte data with odd address is transferred on D15-D8 bus lines.
 The processor provides two enable signals, BHE and A0 for
selection of either even or odd or both the banks.
• The instruction stream is fetched from memory as words and is
addressed internally by the processor as necessary. Witch has
3 possibilities:
1. Both the bytes may be data operands.
2. Both the bytes may contain opcode bits.
3. One of the bytes may be opcode while the other may be
data
• The opcodes and operands are identified by the internal
decoder
• It is always better to locate the word data at an even address.
• To read or write a complete word from/to memory: if it is
located at an even address, only one read or write cycle is
required.
• odd address, the first read or write cycle is required for
accessing the lower byte while the second one is required for
accessing the upper byte.
• the BIU requires one or two memory cycles, depending upon
whether the starting byte is located at an even or odd address
• locations from FFFFOH to FFFFFH are reserved for operations
including jump to initialization program me and I/O-processor
initialization.
• locations 00000H to 003FFH are reserved for interrupt vector
table. The interrupt structure provides space for a total of 256
interrupt vectors.
• each interrupt routine requires 4 bytes for storing it in the
interrupt vector table. Hence 256 types of interrupt require 256
x 4 = 03FFH (1Kbyte) locations
1.3 I/O ADDRESSING CAPABILITY:

• can address up to 64K I/O byte registers or 32K word registers.

• limitation is that the address of an I/O device must not be
greater than 16 bits in size, i.e. maximum number of 216=64
Kbyte I/O devices may be accessed by the CPU.
• (A16 — A19) are at logic 0 level during the IO operations cause
they work as status flags.
• The 16-bit register DX is used as 16-bit I/O address pointer,
• In this case, the IO ports are addressed in the same manner as
memory locations in the based addressing mode using BX.
• Even addressed bytes are transferred on D7—D0 and odd to
D8— D15 lines

1.4 I/O Techniques

• To make the characteristics of I/O devices compatible with

those of the microcomputer, interface hardware circuitry
between the microcomputer and I/O devices is necessary
since the speed of operation of the peripherals is usually
slower compared to the microcomputer, and the word length
of the microcomputer may be different from the data format of
the peripheral device.
• the user gets involved with two types of I/O devices: physical
I/O and logical I/O. When there is no operating system, the user
must work directly with physical I/O devices

There are three ways of transferring data between the

microcomputer and
a physical I/O device:
 1. simple i/o:
if u have simple i/o
i=> thermostat =just connect to input port line
0=> LED=.. .. .. .. output port
2. conditional i/o
HANDSHAKE:
A. Simple strobe i/o:
mainly u sent a stb seg to the micro notifying it that the data is
present at ports and valid when data should be read at a certain
timing.
You can connect this strobe line to an input port line and poll it to
determine when you can input valid data from the keyboard.
Another alternative is to connect the strobe line to an interrupt input
on the processor and have an interrupt service routine read in the
data when the processor receives an interrupt
Strobe has a separate line than data
The point here is that this transfer is time dependent. You can only
read in data when a strobe pulse tells you that the data is valid
for high-speed data transfer this method does not work because
there is no signal which tells the sending device when it is safe to
send the next data byte.
B. Single handshake i/o:
Handshake or strobed input
Same as previous only after data and STB is sent and data is read
the micro sends ACK signal to tell it that it is safe to send the next
byte which is the dis of the previous one
C. double handshake i/o:
For data transfers where even more coordination is required
-The sending device asserts its STB line low to ask. “Are you ready?
The receiving system raises its ACK line high to say, “I'm ready.”
The peripheral device then sends the data and raises Its STB line
high to say. “Here is the data’ After it has read in the data the
receiving system drops its ACK line low to say,
“I have the data, thank you, and I await your request to send the
next unit of data,
3. direct memory access (DMA):
• technique that transfers data between a microcomputer’s
memory and an I/O device without involving the
microprocessor
• used in transferring large blocks of data between a peripheral
device and the microcomputer’s memory.
• The DMA technique uses a DMA controller chip for the data-
transfer operation. The main functions of a typical DMA
controller are summarized as follows:
1. The I/O devices request DMA operation via the DMA request
lines of the controller chip.
2. The controller chip activates the microprocessor HOLD pin,
requesting the CPU to release the bus.
3. The processor sends HLDA (hold acknowledge) back to the
DMA controller, indicating that the bus is disabled. The DMA
controller places the current value of its internal registers,
 such as the address register and counter, on the
system bus and sends a DMA acknowledge to the peripheral
device. The DMA controller completes the DMA transfer and
releases the buses.

Lect 3: INTERRUPTS AND INTERRUPT SERVICE

ROUTINES

diverts its execution to some other program called Interrupt Service

Routine (ISR) in order to service that interrupt.
multiple interrupt processing capability is when processor is able
to handle more than one interrupt at a time
8086 doesn’t have it, If more than one type of INTR interrupt occurs
at a time, then an external chip called programmable interrupt
controller is required to handle them
NMI,INTR,256 types(0 to255) named as numbered and each have
separate interrupt service routine ISR.

Interrupts Sources in 8086:

1. Internal (software)
2. external (hardware)

Interrupts Sources in 8086:

For an indirect call the 8086 gets the new values for CS (code
segment) and IP (instruction pointer) from four memory addresses.
In an 8086 system the first 1 Kbyte of memory from 00000H to
003FFH is set aside as a table for storing the starting addresses of
interrupt service procedures. Since 4 bytes are required to store the
CS and IP values for each interrupt service procedure, the table can
hold the starting addresses for up to 256 Interrupt procedures.
The starting address of an interrupt service procedure stored in this
table is often called the interrupt vector or the interrupt pointer,
and the table itself is then referred to as the interrupt vector table or
the interrupt pointer table.
The lowest five interrupt types are dedicated to specific interrupts
such as the divide by zero interrupt and the non-maskable interrupt
Note that the new value for the instruction pointer is put in as the
low word of the pointer, and the new value for the code segment
register is put in as the high word of the pointer.
The 8086 loads the values of IP and CS from the 20-bit physical
addresses 00008H and 0000AF in the pointer table.
phosical address = cs*10H+ip=20‫خانه‬

Nonmaskable and Maskable Interrupts:

The NMI pin should remain high for at least two clock cycles and is
not needed to be synchronized (cause its non-maskable so the
processor is gonna respond either ways) with the clock for being
sensed. When NMI is activated, the current instruction being
executed is completed, and then the NMI is served.
All software interrupts are nonmaskable interrupts since the
processor is going to respond to such interrupts whatever was the
status of the Interrupt flag (IF)
The INTR signal is level triggered and can be masked by resetting the
interrupt flag. It is internally synchronized with the high transition of
CLK.
If the IF is reset, the processor will not serve any interrupt appearing
at this pin. If the IF is set, the processor is ready to respond to any
INTR interrupt (ACK).

Predefined Interrupts (0 to 4)
DIVISION BY ZERO (type 0), SINGLE STEP (to execute line by line)
(type 1) NONMASKABLE INTERRUPT pin (type 2), BREAKPOINT-
INTERRUPT (type 3), and INTERRUPT ON OVERFLOW (type 4).
1-When the TF (TRAP flag) is set by an instruction, the 8086 goes
into the single step mode
2-Breakpoints are useful program debugging.
3- This interrupt occurs if overflow flag (OF) is set and the INTO
instruction is executed.

Interrupt Response in 8086

The CPU first completes the execution of the current instruction.
The IP is then incremented to point to the next instruction.
 • the programmer must, either externally or through the
program, set the interrupt vector table for that type suitably
with the CS and IP addresses of the interrupt service routine

• me: I hear by declaring assembly out of my curriculum if u got

that much time go read it ur self from each lecture

THE 8255A PROGRAMMABLE PERIPHERAL INTERFACE (PPI):

has 24 I/O pins that can be grouped primarily in two 8-bit parallel
ports:
A and B, with the remaining eight bits as port C. The eight bits of port
C can be used as individual bits or be grouped in two 4-bit ports:
CUPPER (CU) and CLOWER, (CL),

functions of the 8255A, classified

according to two modes:
a. the Bit Set/Reset (BSR) mode
b. the I/O mode.
The BSR mode is used to set or reset
the bits in port C.
The I/O mode is further divided into three modes: Mode 0. Mode 1,
and Mode 2.
1. In Mode 0, all ports function as simple I/O ports. (whole port
not bit by bit)
 2. Mode 1 is a handshake mode whereby ports A and/or B use bits
from port C as handshake signals (c0-c2 is foe port b
handshake c3-c5 for a). In the handshake mode, two type of
I/O data transfer can be implemented: status check and
interrupt.
3. Mode 2, port A can be set up for bidirectional data transfer
using handshake signals
from port C, and port B
can be set up either in
Mode 0 or Mode 1 (c3 to
c7 are used for port a
config for double
handshake
c0-2 are either used for b
in mode 1 or free if b is in
mode 0)

CONTROL LOGIC
The control section has six lines. Their functions and connections
are as follows:
• RD (Read): enables the Read operation. When the signal is low, the
MPU reads data from a selected I/O port of the 8255A.
• WR (Write): enables the Write. When the signal goes low ……etc.
• RESET (Reset): active high signal; it clears the control register and
sets all ports in the input mode.
• CS, A0, and A1: These are device select signals. CS is connected
to a decoded address, and A0 and A1 are generally connected to
MPU address lines A0 and A1, respectively.
The CS signal is the master Chip Select, and A0 and A1 specify one
of the I/O ports or the control register as given below:

Example:
the port addresses in Figure 4.3(a) are determined by the CS, A0,
and A1 lines.
The CS line goes low when A7 = 1 and A6 through A3 are at logic 0,
and A0 is at logic 0. When these signals are combined with A2 and
A1, the port addresses take the even addresses range from 80H to
86H, as shown in Figure 4.3(b)

The contents of this register, called the control word, specify an I/O
function for each port.
This register can be accessed to write a control word when A0 and
A1 are at logic 1. The register is not accessible for a Read operation.
To communicate with peripherals through the 8255A, three steps
are necessary:
1. Determine the addresses of ports A. B, and C and of the control
register according to the Chip Select logic and address lines A0 and
A1.
2. Write a control word in the control register.
3. Write I/O instructions to communicate with peripherals through
ports A, B, and C

Mode-0: Simple Input or Output:

input/output features in Mode 0 are as follows:

1. Outputs are latched.

2. Inputs are not latched.
3. Ports do not have handshake or interrupt capability
‫انا غايتو ما شايل اسمبلي هنا انت شوف ظروفك شنو‪Me:‬‬
BSR (Bit Set/Reset) Mode:
individual bits of port C can be used for applications such as an

on/off switch

LECT9 :TIMER:

The 8254 programmable interval timer/counter is used to:

1. generate accurate time delays
2. applications such as:
A. a real-time clock,
B. an event counter,
C. a digital one-shot,
D. a square-wave generator,
 • The 8254 includes three identical 16-bit counters that can
operate independently in any one of the six modes
• packaged in a 24-pin DIP and requires a single +5 V power
supply.
• To operate a counter, a 16-bit count is loaded in its register
and, on command, begins to decrement the count until it
reaches 0.
• At the end of the count it generates a pulse that can be used to
interrupt the MPU.
• The counter can count either in binary or BCD(binary coded
decimal i.e. each 4 bits represent a decimal number 0-9).
• In addition, a count can be read by the MPU while the counter
is decrementing

Features:
1. Three independent 16-bit count down coumters.
2. 8254 can handle input from DC to 10MHz while 8253 can
handle up to2.6Mhz
3. The three counters are identical presentable and can be
programmed for either binary or BCD count
 4. Counter can be programmed in 6 different modes
5. Compatible with all intel an most of the other micro processors
6. 8254 has a powerful command called READ-BACK witch... Etc.

Three counters- data bus buffer- read/write control logic- control

word reg- each counter has two input (clk, gate), one output (out)
Control word reg: (A1,A0=0)
Specifies the counter to be used, mode, r/w

WRITE Operation:
1. Write a control word into control register.
2. Load the low-order byte of a count in the counter register.
3. Load the high-order byte of count in the counter register.
READ Operation:
three possible methods:
1. Simple Read:
It involves reading a count after inhibiting (stopping) the counter by
controlling the gate input or the clock input of the selected counter,
and two I/O read operations are performed by the CPU. The first I/O
operation reads the low order byte, and the second I/O operation
reads the high order byte.
2. Counter Latch Command:
In the second method, an appropriate control word is written into
the control register to latch a count in the output
latch, and two I/O read operations are performed by the CPU.
3. Read-Back Command (Available only for 8254) :
The third method uses the Read-Back command. This command
allows the user to check the count value,
programmed Mode, and current status of the OUT pin and Null
count flag of the selected counter(s)

TIMER MODES
• GATE OF A COUNTER IS USED EITHER TO DISABLE OR ENABLE
COUNTING
• IN MODE 0, AFTER THE COUNT IS WRITTEN AND IF THE GATE
IS HIGH, THE COUNT IS DECREMENTED EVERY CLOCK
CYCLE. WHEN THE COUNT REACHES ZERO; THE OUTPUT
GOES HIGH AND REMAINS HIGH UNTIL A NEW COUNT OR
 MODE WORD IS LOADED.

WRITE OPERATIONS:

To initialize a counter, the following steps are necessary:

1. Write a control word into the control register.
2. Load the low-order byte of a count in the counter register.
3. Load the high-order byte of a count in the counter register.
READ OPERATIONS
either of two methods.
One method involves reading a count after inhibiting (stopping) the
counter to be read.
second method involves reading a count while the count is in
progress (known as reading on the fly).
‫عامه نحن مش بتوع اسمبلي‬
Tutorial rev:
same as this just change config for a1,a2 to a0,a1 to mach the
numbering requirment like so:

Lect 10: serial I/O USART 8251A:

• . A standard may include such items as assignment of pin

positions for signals, voltage levels, speed of data transfer,
length of cables, and mechanical specifications.
• , data can be transmitted as either current or voltage.
 • in serial i/o u config the character length, the parity check type
which is an extra bit for even or odd parity check, sending rate,
num of stall bit, stop bit they indicate the begin and end of a
character, which is usually low bit to pull the high line down for
a time that is 1,2 or 1.5 which is one and a half pulse
• Typically, 20 mA (or 60 mA) current loops are used in teletype
equipment. The advantage of the current loop method is that
signals are relatively noise-free and are suitable for
transmission over a distance
• When data are transmitted as voltage, the commonly used
standard is known as RS-232C. It is defined in reference to
Data Terminal Equipment (DTE) and Data Communication
Equipment (DCE)-terminal and modem-
• Computer can be considered a terminal or a modem

RS-232C:
• The signals are divided into four groups:
1. data signals,
2. control signals,
3. timing signals,
4. grounds.
• For data lines, the voltage level +3 V to +15 V is defined as logic
0; from 3 V to-15 V is defined as logic 1 (normally, voltage levels
are±12 V). This is negative true logic. However, other signals
(control and timing) are compatible with the TTL level. Because
of incompatibility of the data lines with the TTL logic, voltage
translators, called line drivers and line receivers, are required
to interface TTL logic with the RS-232 signals
The minimum interface between computer and a peripheral
require 3 lines (2,3,7)
The 8251A programmable communication interface:
Control Register: This 16-bit register for a control word consists of
two independent bytes:
1. the first byte is called the mode instruction (word)
2. the second byte is called command instruction (word).
This register can be accessed as an output port when the C/D pin is
high.

Status Register: This input register checks the ready status of a

peripheral. This register is addressed as an input port when the C/D
pin is high, it has the same port address as the control register.

Data Buffer: This bidirectional register can be addressed as an input

port and an output port when the C/D pin is low.
TxD-Transmit Data: Serial bits are transmitted on this line.
TxC-Transmitter Clock: input signal. controls the rate at which bits
are transmitted by the USART. The clock frequency can be 1. 16. or
64 times the baud.
TxRDY: Transmitter Ready: output signal. When it is high. it indicates
that the buffer register is empty and the USART is ready to accept a
byte. It can be used either to interrupt the MPU or to indicate the
status. This signal is reset when a data byte is loaded into the buffer.

TxE-Transmitter Empty: output signal. Logic I on this line indicates

that the output register is empty. This signal is reset when a byte is
transferred from the buffer to the output registers.

RECEIVER SECTION:

The receiver accepts serial data on the RxD line from a peripheral
and converts them into parallel data. The section has two registers:
the receiver input register and the buffer register.
When the RxD line goes low, the control logic assumes it is a Start
bit, waits for half a bit time, and samples the line again. If the line is
still low, the input register accepts the following bits, forms a
character, and loads it into the buffer register. Subsequently, the
parallel byte is transferred to the MPU when requested. In the
asynchronous mode, two input signals and one output signal are
necessary, as described below.

RxD-Receive Data: Bits are received serially on this line and

converted into a parallel byte in the receiver input register.

RxC-Receiver Clock: This is a clock signal that controls the rate at

which bits are received by the USART. In the asynchronous mode,
the clock can be set to 1, 16, or 64 times the baud.

RxRDY-Receiver Ready: This is an output signal. It goes high when

the USART has a character in the buffer register and is ready to
transfer it to the MPU. This line can be used either to indicate the
status or to interrupt the MPU
Mode word format:

Command word format:

Status word format:

To initialize the 8251A in the asynchronous mode, a certain

sequence of control words must be followed.
After a Reset operation (system Reset or through instruction),
• A mode word must be written in the control register followed by a
command word.
• Any control word written into the control register immediately
after a mode word will be interpreted as a command word; that
means a command word can be changed anytime during the
operation.
• However, the 8251A should be reset prior to writing a new mode
word, and it can be reset by using the Internal Reset bit (D6) in
the command word.

Check lect 10 part 2 example : important and only 20 mins