REGISTERS

A Register is a collection of flip flops. A flip flop is used to store single bit digital data. For
storing a large number of bits, the storage capacity is increased by grouping more than one flip
flops. If we want to store an n-bit word, we have to use an n-bit register containing n number of
flip flops.

SHIFT REGISTERS

A Shift Register can shift the bits either to the left or to the right. A Shift Register,
which shifts the bit to the left, is known as "Shift left register", and it shifts the bit to
the right, known as " Shift Right register".

The shift register is classified into the following types:

o Serial In Serial Out

o Serial In Parallel Out
o Parallel In Serial Out
o Parallel In Parallel Out

Serial IN serial OUT

In "Serial Input Serial Output", the data is shifted "IN" or "OUT" serially. Data is entered into the
shift register one bit at a time (serially) and is also retrieved one bit at a time (serially).

Let all the flip-flop be initially in the reset condition i.e. Q3 = Q2 = Q1 = Q0 = 0. If an entry of a four bit binary number 1 1
1 1 is made into the register, this number should be applied to Din bit with the LSB bit applied first. The D input of FF-3 i.e.
D3 is connected to serial data input Din. Output of FF-3 i.e. Q3 is connected to the input of the next flip-flop i.e. D2 and so
on.

Operation
When the clock signal application is disabled, the outputs Y3 Y2 Y1 Y0 = 0000. The LSB bit
of the number is passed to the data input Din, i.e., D3. We will apply the clock, and this
time the value of D3 is 1. The first flip flop, i.e., FF-3, is set, and the word is stored in the
register at the first falling edge of the clock. Now, the stored word is 1000.

The next bit of the binary number, i.e., 1, is passed to the data input D2. The second flip flop, i.e.,
FF-2, is set, and the word is stored when the next negative edge of the clock hits. The stored
word is changed to 1100.

The next bit of the binary number, i.e., 1, is passed to the data input D1, and the clock is applied.
The third flip flop, i.e., FF-1, is set, and the word is stored when the negative edge of the clock
hits again. The stored word is changed to 1110.

Similarly, the last bit of the binary number, i.e., 1, is passed to the data input D0, and the clock is
applied. The last flip flop, i.e., FF-0, is set, and the word is stored when the clock's negative edge
arrives. The stored word is changed to 1111.
Serial IN Parallel OUT
In the "Serial IN Parallel OUT" shift register, the data is passed serially to the flip flop, and
outputs are fetched in a parallel way. Data is loaded bit by bit. The outputs are disabled as long
as the data is loading.

Below is the block diagram of the 4-bit serial in the parallel-out shift register. The circuit
having four D flip-flops contains a clear and clock signal to reset these four flip flops. In SIPO,
the input of the second flip flop is the output of the first flip flop, and so on. The same clock
signal is applied to each flip flop since the flip flops synchronize each other. The parallel outputs
are used for communication.
Parallel IN Serial OUT
In the "Parallel IN Serial OUT" register, the data is entered in a parallel way, and the
outcome comes serially. A four-bit "Parallel IN Serial OUT" register is designed below.
The input of the flip flop is the output of the previous Flip Flop. The inputs are
connected through the combinational circuit. Through this combinational circuit, the
binary input B0, B1, B2, B3 are passed. The shift mode and the load mode are the two
modes in which the "PISO" circuit works.

When shift/load=1 then 1,3,5 AND gate is enable so here serial shifting occurs. when
shift/load=0 then 2,4,6 AND Gate is enable so parallel loading occurs

Shift/load=1 1 shifting 1,3,5 and gate active

Parallel IN Parallel OUT
In "Parallel IN Parallel OUT", the inputs and the outputs come in a parallel way in the
register. The inputs B0, B1, B2, and B3, are directly passed to the data inputs D0, D1, D2,
and D3 of the respective flip flop. The bits of the binary input is loaded to the flip flops
when the negative clock edge is applied. The clock pulse is required for loading all the
bits. At the output side, the loaded bits appear.

Block Diagram

COUNTERS
A Counter is a device which stores (and sometimes displays) the number of
times a particular event or process has occurred.

Counter works in two modes

Up counter
Down counter
Counters are broadly divided into two categories

1. Asynchronous counter
2. Synchronous counter

1. Asynchronous Counter/Ripple counter

In asynchronous counter we don’t use universal clock, only first flip flop is
driven by main clock and the clock input of rest of the following flip flop is driven
by output of previous flip flops. Its design and implementation is very simple

Synchronous Counter
Unlike the asynchronous counter, synchronous counter has one global clock
which drives each flip flop so output changes in parallel. Its design and
implementation are very complex.
 • Explain asynchronous counter/Ripple counter
Asynchronous counters are also known as ripple counters .The number of
output state of the counter is called Modulus or Mod of the counter. The
maximum possible number of output state of a counter is 2n ,where n is the
number of flip flop in that counter. for example if we have 2 flip flop in a
counter then the maximum number of output state of the counter is [Link] can
call that counter as a MOD 4 counter.

4 bit asynchronous counter/4 bit ripple counter

Mod 16 counter consists of 4 JK flip flop . A Mod-16 Counter is a digital counting circuit that
cycles through 16 distinct states, typically counting from 0000 (0) to 1111 (15) in binary and
then resetting back to 0000. The clock is connected to the first flip flop and output of this flip
flop given as a clock input to the next flip flop

Initially the counter is in reset [Link] is Q3Q2Q1Q0=[Link] applying first clock pulse we
get Q3Q2Q1Q0=0001 and then next clock pulse Q3Q2Q1Q0 becomes 0010 and so [Link] applying
last clock pulse we get Q3Q2Q1Q0 =1111, then next state is [Link] here by using 4 bit
asynchronous ripple counter we can count total 16 states from 0000 to 1111.
MOD 10 asynchronous counter/ BCD counter

MOD 10 couter is also known as Decade counter. It requires 4 flip flip(smallest

value of n satisfies 2n condition).so there is 16 possible [Link] of which 10 are
valid and remaining six are invalid.
The counter has 10 stable states 0000 to [Link] is counter from 0 to 9. The
initial state is 0000 and after 9 th clock pulse it goes to 1001. When the 10 th clock
pulse is applied counter goes to state [Link] of the feedback provided it
goes to initial state.

Invalid states= 1010+1011+1100+1101+1110+1111

=Q3Q1(where Q3=1 and Q1=1 then the flip flop goes to reset state, since it
is NANDED and connected to clear input of each flip flop)

4 BIT SYNCHRONOUS COUNTER

A 4-bit synchronous counter is a digital device that counts in a binary sequence from 0 (0000)
to 15 (1111) and then wraps around back to 0. Being synchronous means that all the flip-flops
are driven by a common clock signal, ensuring that all state transitions occur simultaneously.
This leads to faster and more reliable operation compared to asynchronous (ripple) counters

Flip-Flops: These are like small memory units that store 1 bit each. Since it’s a 4-bit
counter, we use four flip-flops, one for each bit

Clock: This sends pulses to the flip-flops to tell them when to change their value (count
up)

Logic Gates: These are used to control when each flip-flop should change its value based
on the current count.
 Working

 At the first clock pulse, the counter shows 0001 (binary for 1).
 At the next pulse, it shows 0010 (binary for 2).
 This keeps going until it reaches 1111 (binary for 15), then it resets back to 0000.

RING COUNTER(4 bit ring counter)

Ring counter is an example of synchronous counter. The above figure shows 4 bit
ring counter using D flip flop. In ring counter the output of last flip flop is
connected to input of first flip [Link] 4 flip flop connected in series. The clock
signal is applied to clock input of each flip flop simultaneously and reset pulse is
applied to the clear input.

When Pr(preset) is 0 then the output is 1 and when clear is 0 then the output is 0.
Initially preset is connected to first flip flop and clear is connected to FF2,FF3,FF4.
Thus the output state is Q=1000. First clock pulse is applied then the content of
first flip flop is shifted to the next Flip Flop, then Q becomes 0100. In next clock
pulse Q becomes 0010 and it becomes 0001. If we again applying clock pulse then
the counter becomes initial stage 1000,because of feedback is provided to the first
flip flop. So the 4 bit ring counter have 4 possible states

1000

0100

0010

0001