Clock Generation and Distribution
Clock Definition and Parameters
Clock-special signal
Clock signals are often regarded as simple control signals; however, these signals have some very special characteristics and attributes. loaded with the greatest fanout, ravel over the longest distances, and operate at the highest speeds of any signal, either control or data, within the entire system.
Integral part of system design
Tradeoffs ---system speed, physical die area, and power dissipation are greatly affected by the clock distribution network. The design methodology and structural topology of the clock distribution network should be considered in the development of a system for distributing the clock signals.
Requirements
clock waveforms must be particularly clean and sharp., No skew
Difficulty
The requirement of distributing a tightly controlled clock signal to each synchronous register on a large hierarchically structured integrated circuit within specific temporal bounds is difficult
Technology scaling
Technology scaling, in that long global interconnect lines become much more highly resistive as line dimensions are decreased. This increased line resistance is one of the primary reasons for the growing importance of clock distribution on synchronous performance.
Clock distribution strategies [only relative phase between two clocking element is important]
Achieve Zero skew routing
Route clock to destinations such that clock edges appear at the same time
Clock tree
Single driver---If the interconnect resistance of the
buffer at the clock source is small as compared to the buffer output resistance,
maintaining high-quality waveform shapes (i.e., short transition times) Use elmore formula to compute delay Balance delay paths Drawback---large delay, drive capability should be high
Terminology
The unique clock source is frequently described as the root of the tree, t he initial portion of the tree as the trunk, individual paths driving each register as the branches, and the registers being driven as the leaves
Buffered clock Tree interconnect resistance large
The most common and general approach to equi-potential clock distribution is the use of buffered trees, It leads to an asymmetric structure ALL PATHS ARE BALANCED
Buffered clock Tree
Insert buffers either at the clock source and/or along a clock path, forming a tree structure.
Buffers
The distributed buffers serve the double function of amplifying the clock signals degraded by the distributed interconnect impedances and isolating the local clock nets from upstream load impedances
DESIGN
All nodes have capacitance All branches have resistance Fix the load (fan out ) of each buffer Compute no .of levels required Position the buffers optimally Guidelines- minimize delay buffer delay=segment delay
3D Skew Visualization
Mesh version of clk tree
Mesh version of clock tree
Shunt paths further down the clock distribution network are placed to minimize the interconnect resistance within the clock tree. This mesh structure effectively places the branch resistances in parallel, minimizing the clock skew.
CDN properties
H TREEsymmetric,regular array, clk skew can be small X TREE- variant of H TREE Zero skew is achieved maintaining the distributed interconnect and buffers to be identical from the clock signal source to the clocked register of each clock path. each clock path from the clock source to a clocked register has practically the same delay.
Skew
The primary delay difference between the clock signal paths is due to variations in process parameters that affect the interconnect impedance and, in particular, any active distributed buffer amplifiers. The amount of clock skew within an H-tree structured clock distribution network is strongly dependent upon the physical size, the control of the semiconductor process, and the degree to which active buffers are distributed within the Htree structure
Tapered H tree
The conductor widths in H-tree structures are designed to progressively decrease as the signal propagates to lower levels of the hierarchy. This strategy minimizes reflections of the high-speed clock signals at the branching points.
H Tree---Difficulty -1
Clock routed in both the vertical and horizontal directions. For a standard twolevel metal CMOS process, this manhattan structure creates added difficulty in routing the clock lines without using either resistive interconnect or multiple high resistance vias between the two metal lines. 3 level metal process
Difficulty -2
Furthermore, the interconnect capacitance (and therefore the power dissipation) is much greater for the H-tree as compared with the standard clock tree since the total wire length tends to be much greater An important tradeoff between clock delay and clock skew in the design of highspeed clock distribution networks.
Grid
Low skew achievable Lots of excess interconnect Large power dissipation
Clock distribution-hierarchical
Distribute global reference to various parts of the chip with zero skew Local distribution of the clock while considering local load variations. , permitted clk skew, . Power saving strategies are used here.
GCLK
Gridded global clock signal (GCLK) is distributed over the entire IC in order to maintain a low-resistance reference clock signal and to distribute the power dissipated by the clock distribution network across the die area The global clock signal GCLK is the source of thousands of buffered and conditional (or gated) clock signals driving registers across the IC
PLL
ps 5 10 15 20 25 30 35 40 45 50
Low power CDN
SPEED
Operate vdd at half rails Data should operate at full rails
Low vdd clock trees
Multiple Supply Voltages
Smaller voltage to distribute the signal over the chip, and then converting this low voltage clock signal back to a higher voltage at the utilization points
A Level Converter Using Multiple Supply Voltages
A Level Converter Using Multiple Supply Voltages
REDUCED SWING APPROACH
Level Converter Using a Reduced Clock Swing
Clock gating
