Electro Static Discharge
in Silicon IC Technologies
ESD
BY : Damodar B. Charate
Outline
Background to ESD
Static Charge Build-up
ESD Failures
ESD Models
ESD Protection
ELECTROSTATIC DISCHARGE
(ESD)
Electrostatic Discharge?
Sudden discharge of a charged body
Importance of ESD to the Semiconductor
Industry
Unexpected destruction of semiconductor
devices
Losses can occur anywhere from fabrication to
field
Millions of $ in real and hidden losses each year
ELECTROSTATIC DISCHARGE
(ESD)
Electrostatic Discharge (ESD) :
The transfer of electrostatic charge between
bodies or surfaces at different electrostatic
potential. ESD is a subset of EOS
Electrical Overstress (EOS):
The exposure of an object to a current or
voltage beyond its maximum ratings
Static Charge Build-Up
Materials Make Intimate Contact
Charge - Separation
TRIBOELECTRIC SERIES
POSITIVE (+)
Human Hands
Rabbit Fur
Glass (Quartz)
Mica
Human Hair
Nylon
Wool
Fur
Lead
Silk
Aluminum
Paper
Cotton
Steel
Wood
Amber
Sealing Wax
Hard Rubber
Nickel, Copper
Brass, Silver
Gold, Platinum
Sulfur
Acetate Rayon
Polyester
Celluloid
Orlon
Polyurethane
Polyethylene
Polypropylene
PVC
KEL F
Silicon
Teflon
NEGATIVE (-)
ESD Failure
ESD DAMAGE TO ICs
Any point from manufacture to field service
Handling the devices in uncontrolled
surroundings
Poor ESD control practices used
Types of Failure:
Catastrophic failure
Latent failure
What Causes Electronic
Devices to Fail?
Discharge to the Device
Discharge from the Device
Field Induced Discharges
What Fails?
Oxide breakdown of the transistor gates
(CDM)
Thermal in nature to the transistor junctions
(MM and HBM)
Metallization and Poly-silicon Burn-out
Hot-carrier injection
Oxide breakdown
Gate oxide damage in MOS transistor after the CDM stress
Junction Breakdown
Drain junction filamentation in MOS transistor due to the ESD stress
Metallization and Poly-silicon
Burn-out
Interconnects damage due to the ESD stress
Hot-carrier injection
Mechanism of charge injection in gate oxide region under ESD stress
ESD Model
ESD Model
Human Body Model or HBM
Machine Model or MM
Human handling of the chips)
Robotic handling in assemblies
Charged Device Model or CDM
Charge from the package itself
HBM
MM
CDM
ESD Waveform
ESD Protection
ESD PROTECTION IS ONLY AS STRONG AS THE
WEAKEST LINK!
ON Chip ESD Protection
Full Chip ESD Protection
ESD protection between power
Protection circuits for I/O pins
ESD Testing
Zapping modes: (a) PS-mode (b) NS-mode (c) PD-mode (d) ND-mode
How to Protect an IO IN ESD
Event
ESD protection required for a
typical IO PAD
ESD Protection on a IO PAD
How it works???
PAD to VDD (PD)
VSS to PAD (NS)
PAD to VSS (PS)
VDD to PAD (ND)
ESD Between IOs
RC Triggered Clamp
Snap Back Clamp
Grounded Gate NMOS in Snap Back Mode
Snap Based ESD Protection
Snap Based ESD Protection
A typical Input Signal PAD
RBUS
LV
LOCAL
CLAMP
P
PAD
RBUS
RBUS
VDDO
(RAIL)
RBUS
IO DEVICE
CORE
SIDE
LV
LOCAL
CLAMP
VSSO (RAIL)
RBUS
RBUS
RBUS
ESD Paths Between Diff Power
VDDO2V5
VSS
VDD
VSSO
VDD
VDDO3V3
VSSO
VDDO2V5
LV
CLAMP
VDDO3V3
Back to
Back
Diodes
LV
CLAMP
HV
CLAMP
HV
CLAMP
VSS
VSS
VDD
2.5V domain
VDD
3.3V domain
ESD protection in a
bidirectional I/O circuit.
Full Chip Wire Bond
LVTTL
DDR
LVTTL
LVDS
LVDS
LV
DS
DDR
LVTTL
S1 S2
S3
S4 S5
VDD
BUS
VSS
BUS
BUS
S6
VDDO
PAD
VDDO
(3.3V)
VSSO
PAD
BUS
VSS
PAD
VDDO
(2.5V)
VDD
PAD
VDDO
PAD
VSSO
PAD
VSS
PAD
VDD
PAD
VSSO BUS
A typical CMOS buffer stage (a) schematic (b) cross section
A typical CMOS Receiver (a) schematic (b) cross section
Layout Issues
