ECE-E434 Digital Electronics
Lectures 10-12: Pass-transistor Logic,
Dynamic Logic, Memory Circuits
Instructor: Pouya Dianat
Oct 31 & Nov 2-3 2017
ECE-E434
Digital Electronics
Advanced Topics in Digital IC Design – Ch. 15
Digital IC Technologies
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ECE-E434
Digital Electronics
Advanced Topics in Digital IC Design – Ch. 15
Pass-Transistor Logic (PTL)
A B C Y A B C Y
H H H H H H H H
L H H L L H H L
H L H L H L H H
H H L L H H L H
H L L L H L L L
L H L L L H L L
L L H L L L H L
L L L L L L L L
Y = ABC Y = A (B + C)
ECE-E434
Digital Electronics
Advanced Topics in Digital IC Design – Ch. 15
Pass-Transistor Logic (PTL)
Main benefit: Lower number of transistors per operation than CMOS alone.
CMOS-transmission Gate
ECE-E434
Digital Electronics
Advanced Topics in Digital IC Design – Ch. 15
PTL Design Consideration
A basic design requirement of PTL circuits:
• every node must have, at all times, a low-resistance path to either ground or
VDD.
Such a path does not exist It is provided through switch S2.
when B is low and S1 is open.
ECE-E434
Digital Electronics
Advanced Topics in Digital IC Design – Ch. 15
An example of NMOS TPL
ECE-E434
Digital Electronics
Advanced Topics in Digital IC Design – Ch. 15
Reminder: The body effect
The body effect can be seen as a change/increase in threshold voltage
ECE-E434
Digital Electronics
Advanced Topics in Digital IC Design – Ch. 15
Dynamic Response of NMOS PTL
• Reduced gate noise immunity
• “Poor 1” Operation Can cause conduction in the next inverter
ECE-E434
Digital Electronics
Advanced Topics in Digital IC Design – Ch. 15
Solution to NMOS PTL Problem
ECE-E434
Digital Electronics
Advanced Topics in Digital IC Design – Ch. 15
ECE-E434
Digital Electronics
Advanced Topics in Digital IC Design – Ch. 15
CMOS Transmission Gate Logic
ECE-E434
Digital Electronics
Advanced Topics in Digital IC Design – Ch. 15
CMOS Pass Logic: Dynamic Response
ECE-E434
Digital Electronics
Advanced Topics in Digital IC Design – Ch. 15
Equivalent resistance:
ECE-E434
Digital Electronics
Advanced Topics in Digital IC Design – Ch. 15
Time Response
ECE-E434
Digital Electronics
Advanced Topics in Digital IC Design – Ch. 15
Equivalent Capacitance
ECE-E434
Digital Electronics
Advanced Topics in Digital IC Design – Ch. 15
Logic Circuits with PTL
ECE-E434
Digital Electronics
Advanced Topics in Digital IC Design – Ch. 15
Dynamic MOS Circuit
• Static Circuits Every node has a defined low (ground) or high (VDD) voltage
• Dynamic Circuits Relies on charging of capacitors
• Problems: Caps may be leaky; therefore nodes lose voltage
• Solution: Periodically refreshing node voltages with a clock signal
ECE-E434
Digital Electronics
Advanced Topics in Digital IC Design – Ch. 15
Why Dynamic MOS Logic
Standard CMOS: Psuedo-NMOS: PTL: Dynamic MOS Logic:
• Easy to design • Simpe small area • Complex non-
• Max logic swing • Requires CMOS to robust design
• Noise-immune restore voltage
• Zero static power • Non-Zero static • Zero static power
• Equal LH and HL power
delays
• Two transistor per • Two transistor per • Low device count
input input
ECE-E434
Digital Electronics
Advanced Topics in Digital IC Design – Ch. 15
Dynamic MOS Circuit
• What happens when f is low?
Qp is on, Qe is off No pass to ground
CL charges to VDD
Inputs A, B, and C are allowed to change
ECE-E434
Digital Electronics
Advanced Topics in Digital IC Design – Ch. 15
Dynamic MOS Circuit
• What happens when f is high?
Qp is off, Qe is on
If PDN is high, nothing changes tPLH=0
If PDN is low, CL will discharge tPHL>0; calculated similar to CMOS
• Question: Does Qe increase the delay?
ECE-E434
Digital Electronics
Advanced Topics in Digital IC Design – Ch. 15
Dynamic MOS Circuit: Transistor Sizing
• PDN: follows the same rules as that of CMOS Logic Gates
• Qp :
• W/L should be large enough to charge CL to VDD during the pre-charge interval
• It should be small enough to keep CL small.
ECE-E434
Digital Electronics
Advanced Topics in Digital IC Design – Ch. 15
Dynamic MOS Circuit: Non-idealities
• Noise margin:
• During Evaluation, Qe will conduct.
ECE-E434
Digital Electronics
Advanced Topics in Digital IC Design – Ch. 15
Dynamic MOS Circuit: Non-idealities
• Output voltage decay due to leakage:
• There is leakage current that discharges capacitor
• It is through reverse saturation current of drain-substrate pn junctions (10-15-
10-12A)
• It is temperature dependent
• More significant in slow clock
• Requires “refreshing”
ECE-E434
Digital Electronics
Advanced Topics in Digital IC Design – Ch. 15
Dynamic MOS Circuit: Non-idealities
• Charge sharing: • Static Power Loss
• Fixes charge sharing
• Decreases load cap.
ECE-E434
Digital Electronics
Advanced Topics in Digital IC Design – Ch. 15
Dynamic MOS Circuit: Non-idealities
• Clock feedthrough:
• When Qp turns off
• CL is capacitively coupled to the clock
• Assume PDN is also off Output node is floating
• CL will get charged through the clock signal.
ECE-E434
Digital Electronics
Advanced Topics in Digital IC Design – Ch. 15
Dynamic MOS Circuit: Non-idealities
• Impractical Cascading Problem:
ECE-E434
Digital Electronics
Advanced Topics in Digital IC Design – Ch. 15
Solution to Cascading: Domino Gate
• A standard CMOS is added to prevent premature discharging of CL2
• Disadvantage: Increased Delay is LH transistion.
