Digital Electronics
Logic Gates: using TTL
Part: 1
Prepared by: Md. Shahariar Parvez
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TTL Logic
• The original basic TTL gate was a slight improvement over the DTL gate.
• The propagation delay of a transistor circuit that goes into saturation depends mostly on two factors: storage
time and RC time constants.
• Reducing the storage time decreases the propagation delay. [ RC T P ]
• Reducing resistor values in the circuit reduces the RC time constants and decreases the propagation delay.
• Of course, the trade-off is higher power dissipation because lower resistances draw more current from the
power supply. The speed of the gate is inversely proportional to the propagation delay.
• In the low-power TTL gate, the resistor values are higher than in the standard gate to reduce the power
dissipation, but the propagation delay is increased. [ R so PD but TP ]
• In the high-speed TTL gate, resistor values are lowered to reduce the propagation delay, but the power
dissipation is increased. . [ R so TP but PD ]
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TTL Logic
• The Schottky TTL gate was the next improvement in the technology.
• The effect of the Schottky transistor is to remove the storage time delay by preventing the transistor from
going into saturation.
• The low-power Schottky TTL sacrifices some speed for reduced power dissipation.
• It is equal to the standard TTL in propagation delay, but has only one fifth the power dissipation
• Recent innovations have led to the development of the advanced Schottky series.
• The advanced low-power Schottky has the lowest speed-power product and is the most efficient series. It is
replacing all other low· power versions in new designs.
• TTL gates in all the available series come in three different types of output configuration:
1. Open -collector output
2. Totem-pole output
3. Three-state (or tristate) output
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Open Collector Output (NAND)
• The multiple emitters in transistor Q1 are connected to the inputs.
These emitters behave most of the time like the input diodes in the
DTL gate since they form a pn junction with their common base.
• The base-collector junction of Q1 acts as another pn junction
diode corresponding to D1 in the DTL gate.
• Transistor Q2 replaces the second diode, D2, in the DTL gate.
The output of the TTL gate is taken from the open collector of Q3.
• A resistor connected to Vcc must be inserted external to the IC
package for the output to "pull up" to the high voltage level when
Q 3 is off; otherwise, the output acts as an open circuit.
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Open Collector Output (NAND)
Condition: Circuit
For Q3 to start conducting, the path from Q1 to Q3
must overcome.
= One diode drop in B-C junction of Q1 + two VBE
drop in Q2 & Q3 = 3 × 0.7 = 2.1 V
Operation:
Input Transistor & Diode Output
Status
Any Input = Corresponding BE junction of Q1 is VBE (Q1)=0.9 V.
Low(0.2V) forward biased. Voltage at base of So,Q2& Q3 Cutoff.
Q1 = 0.2V (I/P) + 0.7 V (V BE)= 0.9V Y = Vcc = 5 V (High)
All input = All BE junction of Q1 is reversed VBE (Q1)=2.1 V.
High (5 V) biased. Q2 & Q3 saturation region. So,Q2& Q3 Saturates.
Y = VCE(Q3) = 0.2V (Low)
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Open Collector Output (NAND)
Open-collector gates are used in three major applications:
1. Driving a lamp or relay
2. Performing wired logic
3. Construction of a common-bus system.
External resistor advantage:
• Without an external resistor, the output of the gate will be an open circuit when Q3 is off. An open circuit to
an input of a TTL gate behaves as if it has a high-level input (but a small amount of noise can change this to a
low level).
• So, External resistor is recommended because of the low noise immunity encountered.
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Totem pole Output (NAND)
• The output impedance of a gate is normally a resistive plus a capacitive load.
• The capacitive load consists of the capacitance of the output transistor, the capacitance of the fan-out gates,
and any stray wiring capacitance.
• When the output changes from the low to the high state, the output transistor of the gate goes from
saturation to cutoff and the total load capacitance, C, charges exponentially from the low to the high voltage
level with a time constant equal to RC.
• For the open-collector gate, R is the external resistor marked RL.
typical operating value C = 15 pF and RL = 4 kΩ. Propagation delay, tP = 35ns.
• With an active pull-up circuit replacing the passive pull-up resistor RL , the propagation delay is reduced
to 10 ns.
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Totem pole Output (NAND)
Condition Circuit
• The reason for placing the diode in the circuit is to provide a diode drop in
the output path and thus ensure that Q4 is cut off when Q3 is saturated.
• For Q3 to start conducting, the path from Q1 to Q3 must overcome.
= One diode drop in B-C junction of Q1 + two VBE
drop in Q2 & Q3 = 3 × 0.7 = 2.1 V
• To conduct Q4, base voltage must have = 0.7 (VBE of Q4)+ 0.7 (D1) = 1.4 V.
Input Transistor & Diode Output
Status
Any Input = Corresponding BE junction of Q1 is • Q2& Q3 Cutoff.
Low(0.2V) forward biased. Voltage at base of • Q4 Conducts. D1 Forward biased.
Q1 = 0.2V (I/P) + 0.7 V (V BE)= 0.9V • Y = (High)
Voltage at base of Q2 = 5V
All input = All BE junction of Q1 is reversed VBE (Q1)=2.1 V. So,Q2& Q3 Saturates.
High (5 V) biased. Q2 & Q3 saturation region. VB (Q4) = 0.9V . So, Q4 cutoff.
Q4 Cutoff region. Y = VCE(Q3) = 0.2V (Low)
**This configuration is called a totem-pole output because
transistor Q4 "sits" upon Q3.
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Totem pole Output (NAND)
Advantage of totem pole output:
• When the output changes to the high state because one of the inputs drops to the low state, transistors Q2
and Q3 go into cutoff. However, the output remains momentarily low because the voltages across the load
capacitance cannot change instantaneously.
• The current needed to charge the load capacitance causes Q4 to momentarily saturate, and the output
voltage rises with a time constant RC.
• But R in this case is equal to 130Ω, plus the saturation resistance of Q4, plus the resistance of the diode, for a
total of approximately 150Ω.
• This value of R is much smaller than the passive pull-up resistance used in the open-collector circuit.
• As a consequence, the transition from the low to high level is much faster.
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References
1. Thomas L. Floyd, “Digital Fundamentals” 8th edition, Prentice Hall – Pearson Education.
2. M. Morris Mano, “Digital Logic & Computer Design” Prentice Hall
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