CS325 Operating Systems
Spring 2021
Computer-System Structures
Owais Hakeem
SST
05/27/2021 Operating System, Owais Hakeem, 1
UMT
Agenda for Today
Review of previous lecture
Interrupts
traps, and signals
CPU, and I/O protection
Memory protection
Operating system components
Operating system services
Recap of the lecture
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Interrupts, Traps, and Signals
The occurrence of an event is
usually signaled by an interrupt
from either the
hardware or the
software.
Hardware may trigger an interrupt at
any time by sending a signal to the
CPU usually by way of the system
bus. Answer
Software may trigger an interrupt the Phone
by executing a special operation .
called a system call. .
.
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UMT Resume
Interrupts, Traps, and Signals
A process can generate a trap, for example, by
dividing a number by zero.
A user or a process may generate a signal (an
interrupt to a process)
Answer
the Phone
.
.
.
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UMT Resume
Handling Device Events
• Hardware devices produces events at times and in patterns
not known in advance
– Keyboard presses
– Incoming networks packets
– Mouse movements
– Other events
• How is information generated by these events transmitted
to running applications?
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Two Input Options
• Polling
– OS periodically queries each device to see if
new information is available
• Interrupts
– Device sends a signal to the OS to request
attention
– OS preempts running process to handle device
request
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Polling
• OS periodically asks (polls) each device for event
information
• If an event has occurred, OS retrieves event
information (e.g keyboard keys pressed) from H/W
• Simple design OS periodically checks each H/W
device
• High latency: Device input must wait for polling
interval
– Shortening polling interval leads to inefficiency, since
system must spend a lot of time checking idle devices
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Interrupts
• Hardware devices signal OS when events occur
• OS preempts any running process (switches
context away from the running process) to handle
the event
• Allows for a more responsive system than would
be available with polling
• More complex implementation (requires H/W
support)
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Interrupt Vector
Interrupt transfers control to the interrupt service routine,
generally, through the interrupt vector, which contains
addresses of all the interrupt service routines.
Interrupt architecture must save the address of the
instruction after the interrupted instruction and the CPU
state so that execution of the interrupted process may
continue after the interrupt has been serviced.
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Interrupt Handling …
Incoming interrupts are disabled while another
interrupt is being processed to prevent lost interrupts.
An operating system is interrupt driven.
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Hardware Protection
Dual-Mode Operation
I/O Protection
Memory Protection
CPU Protection
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Dual-Mode Operation
Sharing system resources requires operating system
to ensure that an incorrect program cannot cause
other programs to execute incorrectly.
Provide hardware support to differentiate between at
least two modes of operations.
User mode – execution done on behalf of a user.
Monitor mode (also kernel mode or system
mode) – execution done on behalf of operating
system.
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Dual-Mode Operation …
Mode bit added to computer hardware to indicate the
current mode: monitor (0) or user (1).
When an interrupt or fault occurs hardware switches
to monitor mode.
Interrupt/fault
monitor user
set user mode
Privileged instructions can be issued only in monitor mode.
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I/O Protection
All I/O instructions are privileged instructions.
Must ensure that a user program could never gain
control of the computer in monitor mode (i.e., a user
program that, as part of its execution, stores a new
address in the interrupt vector).
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Memory Protection
Must provide memory protection outside the address
space of a process.
In order to have memory protection, add two registers
that determine the range of legal addresses a program
may access:
Base register – holds the smallest legal physical
memory address.
Limit register – contains the size of the range
Memory outside the defined range is protected.
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Use of Base and Limit Register
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Hardware Support
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CPU Protection
• Timer and a fixed interval clock that
interrupts the CPU periodically
– Timer is loaded with a value and decremented
every clock tick
– When timer reaches the value 0, an interrupt
occurs and an ISR is executed to switch CPU to
another process.
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CPU Protection
Timer – interrupts computer after specified period to
ensure operating system maintains control.
Timer is decremented every clock tick.
When timer reaches the value 0, an interrupt occurs.
Timer commonly used to implement time sharing.
Time also used to compute the current time.
Load-timer is a privileged instruction.
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OS Components
Process management
Main memory management
Secondary storage management
I/O system management
File management
Protection system
Networking
Command-line interpreter (shells)
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Operating System Services
Services for user and users of programs:
Program execution
I/O Operations
File System Manipulation
Communications between processes/users
Error detection and handling
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Operating System Services …
Services for efficient system operation:
Resource management
Accounting
Protection
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Next time
• Operating Systems Kernel
• System calls
• Types of System calls
• System call execution
• Operating system structure
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