ECE 465
Introduction to CPLDs and FPGAs
Shantanu Dutt
ECE Dept.
University of Illinois at Chicago
Acknowledgement: Extracted from lecture notes of Dr. Mohamed M.
Elkhatib, German University of Cairo and Prof. Russell Tessier, Univ. of
Massachusetts. Some modfications and additions done by Prof. Dutt.
CPLD Families
CPLD Block Diagram
1
FF 0
FF
0
FF
FF
FF
0 1
An individual switch
In a crossbar is a
diamond switch
O/Ps
Programmable switch
Function block (~ PLA w/ 1 o/p
for interconnecting
I/Ps that can be FF’ed)
various FBs
Crossbar Switch
CPLD Function Block
Extra function (e.g., g,
h) i/ps for OR term
2:1 Mux
Example function
f= ab+bc’+g+h
D-FF
PLA-like AND array
Literal inputs (e.g., a, b, c)
Field Programmable Gate Arrays (FPGAs)
FPGA Types
(Anti-fuse technology)
FPGA Families
SRAM-type FPGA Interconnect Architecture
Diamond
switch
Horizontal
routing
(interconnect)
channel
PSM: Programmable Switch Matrix (for
making connections between interconnects
of different channels). The structure shown
only allows i-to-i connections
Vertical
routing
channels CLB: Configuration Logic Block
(programmable logic cell)
SRAM-type FPGA Interconnect
Architecture (contd)
Cell Connection
Matrix (CCM)
PSM
Configuration Logic Block (CLB)
• 5-i/p function implemented using G, F and H LUTs (Look Up Tables) using Shannon’s
Expansion: p(a,b,c,d,e) = a p(1, b, c, d, e) + a’ p(0, b, c, d, e) = a q(b,c,d,e) + a’r(b,c,d,e).
q( ) impl. using LUT G, r impl. using LUT F and p=ag + a’h impl. using LUT H
• The LUT o/ps can go through a FF (for seq. ckt design) or bypass it for a combinational o/p
• This is called technology mapping: mapping the logic to CLB logic components
Technology Mapping
Programming a CLB (contd)
Components of Modern FPGAs
Digital System: Implementation Spectrum
Microprocessor Reconfigurable ASIC
Hardware
Software Firmware Hardware
– ASIC gives high performance at cost of
inflexibility.
– Processor is very flexible but not tuned to the
application.
– Reconfigurable hardware is a nice
compromise.
Simplified FPGA Logic Element
Inputs Look-Up Out
Table
(LUT)
State
Clock
Enable
High-level Compilers & FPGAs
–Difficult to estimate hardware resources.
–Some parts of program more appropriate for
processor (hardware/software codesign).
–Compiler must parallelize computation
across many resources.
–Engineers like to write in C/VHDL/Verilog
rather than pushing little blocks around.
for (i = 0; i<n, i++)
{
c[i] = a[i] + b[i]
}
Some success stories
Translating a Design to an FPGA
RTL Circuit Array
. A
. + C
B
C = A+B
.
– CAD to translate circuit from text description to
physical implementation well understood.
– Most current FPGA designers use register-
transfer level specification (allocation and
scheduling)
– Same basic steps as ASIC design.
Circuit Compilation & Implementation:
Basic Steps
1. Technology Mapping
LUT
4. Convert all implementation
LUT “details” to FPGA programming
2. Placement
info (configuration bits): LUT
RAM bits, CCM & PSM
? FF/SRAM bits, etc.
• Can store config bits on disk or ROM and
Assign a logical LUT to a physical load into FPGA as needed
location. • Can thus use the FPGA to implement
multiple digital systems (at different times
or sometimes simultaneously in different
3. Routing FPGA partitions)
Select wire segments
and switches for
Interconnection.
Technology Mapping: A Simple Example
Made of Full Adders
A B A+B = D
Co FA Ci
S
Logic synthesis tool reduces circuit to
SOP form
S = ABCi + ABCi + ABCi + ABCi
A A
B LUT Co B LUT S
Ci Ci
Co = ABCi + ABCi + ABCi + ABCi
Processor + FPGA
Three possibilities
daughtercard
Proc FPGA
chip
Backplane bus
(e.g. PCI)
1. FPGA serves as coprocessor for data
intensive applications – possible project.
Proc FPGA chip
2. FPGA serves as embedded digital system
for lower latency processing. “Reconfigurable Functional Unit”
