Chapter 2

Flip-Flop and Related

Devices

Chapter 2 Prepared by: Pn Siti Zura A. Jalil 1

 Introduction
• Logic circuits studied so far have outputs that respond
immediately to inputs at some instant in time.
• We now introduce the concept of memory. The flip-flop,
abbreviated FF, is a key memory element.
• The outputs of a flip flop are Q and Q’.
• Q is understood to be the normal output, while Q’ is
always the opposite.
• When the normal output (Q) is placed in the high or 1 state
we say the FF has been SET.
• When the normal output (Q) is placed in the low or 0 state
we say the FF has been cleared or RESET.

Chapter 2 Prepared by: Pn Siti Zura A. Jalil 2

 General flip-flop symbol and definition
of its two possible output states.

Chapter 2 Prepared by: Pn Siti Zura A. Jalil 3

 Latch
• Latch is a type of temporary storage device.

• It has two stable state, thus it is a bistable logic

devices / multivibrator, same as the flip-flop.

• Different with the flip-flop is the method used for

changing their output state, where the latches are
not depend to the clock input.

Chapter 2 Prepared by: Pn Siti Zura A. Jalil 4

 NAND Gate Latch
• The NAND gate latch or simply latch is a
basic FF.
• The inputs are set and clear (reset).
• The inputs are active low, that is, the output
will change when the input is pulsed low.
• When the latch is set
Q  1 and Q  0

• When the latch is clear or reset

Q  0 and Q  1

Chapter 2 Prepared by: Pn Siti Zura A. Jalil 5

 A NAND latch has two possible resting
states when SET = CLEAR = 1.

Chapter 2 Prepared by: Pn Siti Zura A. Jalil 6

 Pulsing the SET input to the 0 state when
(a) Q = 0 prior to SET pulse;
(b) Q = 1 prior to SET pulse.
Note that, in both cases, Q ends up HIGH.

Chapter 2 Prepared by: Pn Siti Zura A. Jalil 7

 Pulsing the CLEAR input to the LOW state when
(a) Q = 0 prior to CLEAR pulse;
(b) Q = 1 prior to CLEAR pulse.
In each case, Q ends up LOW.

Chapter 2 Prepared by: Pn Siti Zura A. Jalil 8

 NAND Gate Latch
• Summary of the NAND latch:
– Set = clear = 1. Normal resting state, outputs remain in
state prior to input.
– Set = 0, clear = 1. Q will go high and remain high even
if the set input goes high.
– Set = 1, clear = 0. Q will go low and remain low even
if the clear input goes high.
– Set = clear = 0. Output is unpredictable because the
latch is being set and cleared at the same time.

Chapter 2 Prepared by: Pn Siti Zura A. Jalil 9

 (a) NAND latch; (b) truth table.

Chapter 2 Prepared by: Pn Siti Zura A. Jalil 10

 Alternative gates representations
of NAND gates

Chapter 2 Prepared by: Pn Siti Zura A. Jalil 11

Example 5-1: Assume initially Q = 0

Chapter 2 Prepared by: Pn Siti Zura A. Jalil 12

 Application Example

(a) Mechanical contact bounce will produce multiple

transitions; (b) NAND latch used to debounce a mechanical
switch.
Chapter 2 Prepared by: Pn Siti Zura A. Jalil 13
 NOR Gate Latch
• The NOR latch is similar to the NAND latch
Q and Q
except that the outputs are reversed.
• The set and clear inputs are active high, that is, the
output will change when the input is pulsed high.
• In order to ensure that a FF begins operation at a
known level, a pulse may be applied to the set or
clear inputs when a device is powered up.

Chapter 2 Prepared by: Pn Siti Zura A. Jalil 14

 (a) NOR gate latch; (b) truth table;
(c) simplified block symbol.

Chapter 2 Prepared by: Pn Siti Zura A. Jalil 15

Example 5-1: Assume initially Q = 0

Chapter 2 Prepared by: Pn Siti Zura A. Jalil 16

 Application Example

Chapter 2 Prepared by: Pn Siti Zura A. Jalil 17

 The 74LS279 Quad S-R latch

Chapter 2 Prepared by: Pn Siti Zura A. Jalil 18

 S-R Latch with an EN input
• It has an extra input, called enable (EN)
input line, to control the output.
• The output depend to the S-R input only
when EN is high.
• When EN input is low, the output will be no
change (follow the previous output).

Chapter 2 Prepared by: Pn Siti Zura A. Jalil 19

 A S-R latch

Chapter 2 Prepared by: Pn Siti Zura A. Jalil 20

 QUESTION 1
Determine the Q output waveform for a input applied
to a gated S-R latch that is initially RESET.

Chapter 2 Prepared by: Pn Siti Zura A. Jalil 21

 D Latch (Transparent Latch)
• One data input.
• It has an enable input line, to control the
output.
• The output follows the input only when EN
is high.
• When EN input is low, the output will be no
change.
Chapter 2 Prepared by: Pn Siti Zura A. Jalil 22
D latch: (a) structure; (b) truth table; (c) logic symbol.

Chapter 2 Prepared by: Pn Siti Zura A. Jalil 23

Waveforms for Example 5-7 showing the two modes
of operation of the transparent D latch.

Chapter 2 Prepared by: Pn Siti Zura A. Jalil 24

QUESTION 2
Determine the Q output waveform for a input applied
to a gated D latch that is initially RESET.

Chapter 2 Prepared by: Pn Siti Zura A. Jalil 25

 The 74LS75 Quad gated D latches

Chapter 2 Prepared by: Pn Siti Zura A. Jalil 26

Clock Signals and Clocked Flip-Flops
• Asynchronous system – outputs can change state
at any time the input(s) change.
• Synchronous system – output can change state
only at a specific time in the clock cycle.
– The clock signal is a rectangular pulse train or square
wave.
– Positive going transition (PGT) – when clock pulse
goes from 0 to 1.
– Negative going transition (NGT) – when clock pulse
goes from 1 to 0.

Chapter 2 Prepared by: Pn Siti Zura A. Jalil 27

 Clocked FFs have a clock input (CLK) that is active
on either (a) the PGT or (b) the NGT.
The control inputs determine the effect of the active
clock transition.

Chapter 2 Prepared by: Pn Siti Zura A. Jalil 28

 Clocked S-C Flip-Flop
• The set-clear (or set-reset) FF will change
states at the positive going or negative
going clock edge.

Chapter 2 Prepared by: Pn Siti Zura A. Jalil 29

 a) Clocked S-C flip-flop that responds only to the
positive-going edge of a clock pulse;
(b) truth table; (c) typical waveforms.

Chapter 2 Prepared by: Pn Siti Zura A. Jalil 30

Simplified version of the internal circuitry for
an edge-triggered S-C flip-flop.

Chapter 2 Prepared by: Pn Siti Zura A. Jalil 31

 Clocked J-K Flip-Flop
• Operates like the S-C FF. J is set, K is clear.
• When J and K are both high the output is toggled
from whatever state it is in to the opposite state.
• May be positive going or negative going clock
trigger.
• Has the ability to do everything the S-C FF does,
plus operate in toggle mode.

Chapter 2 Prepared by: Pn Siti Zura A. Jalil 32

 (a) Clocked J-K flip-flop that responds only to the
positive edge of the clock; (b) waveforms.

Chapter 2 Prepared by: Pn Siti Zura A. Jalil 33

 J-K flip-flop that triggers only on
negative-going transitions

Chapter 2 Prepared by: Pn Siti Zura A. Jalil 34

 Internal circuit of the edge-triggered J-K
flip-flop.

Chapter 2 Prepared by: Pn Siti Zura A. Jalil 35

 Clocked D Flip-Flop
• One data input.
• The output changes to the value of the input
at either the positive going or negative
going clock trigger.
• May be implemented with a J-K FF by
tying the J input to the K input through an
inverter.
• Useful for parallel data transfer.
Chapter 2 Prepared by: Pn Siti Zura A. Jalil 36
 (a) D flip-flop that triggers only on positive-going
transitions; (b) waveforms.

Chapter 2 Prepared by: Pn Siti Zura A. Jalil 37

 Edge-triggered D flip-flop
implementation from a J-K flip-flop.

Chapter 2 Prepared by: Pn Siti Zura A. Jalil 38

 Application : Parallel transfer of binary data
using D flip-flops.

Chapter 2 Prepared by: Pn Siti Zura A. Jalil 39

 Asynchronous Inputs
• Inputs that depend on the clock are synchronous.
• Most clocked FFs have asynchronous inputs that
do not depend on the clock.
• The labels PRE and CLR are used for
asynchronous inputs.
• Active low asynchronous inputs will have a bar
over the labels and inversion bubbles.
• If the asynchronous inputs are not used they will
be tied to their inactive state.
Chapter 2 Prepared by: Pn Siti Zura A. Jalil 40
 Asynchronous Inputs (PRE & CLR)
• Active-Low asynchronous inputs
– This input is active when has low (0) input.
– PRE = 0 , CLR = 0.
• Active-High asynchronous inputs
– This input is active when has high (1) input.
– PRE = 1 , CLR = 1.
• When asynchronous inputs is active:
– If PRE input is active : the flip-flop will SET.
– If CLR input is active : the flip-flop will RESET.

Chapter 2 Prepared by: Pn Siti Zura A. Jalil 41

 Clocked J-K flip-flop with Active-Low
asynchronous inputs.

Chapter 2 Prepared by: Pn Siti Zura A. Jalil 42

Waveforms for Example 5-9 showing how a clocked
flip-flop responds to asynchronous inputs.

Chapter 2 Prepared by: Pn Siti Zura A. Jalil 43

 IEEE/ANSI symbols for (a) a single edge-triggered
J-K flip-flop and (b) an actual IC (74LS112 dual
negative-edge-triggered J-K flip-flop).

Chapter 2 Prepared by: Pn Siti Zura A. Jalil 44

IEEE/ANSI symbols for (a) a single edge-triggered
D flip-flop and (b) an actual IC (74HC175 quad flip-
flop with common clock and clear).

Chapter 2 Prepared by: Pn Siti Zura A. Jalil 45

 Master/Slave Flip-Flops
• These devices are obsolete but may be
found in older equipment.
• Generally, these devices can be analyzed as
a negative edge triggered FF.

Chapter 2 Prepared by: Pn Siti Zura A. Jalil 46

 Master/Slave J-K Flip-Flops
• Composed 2 sections: Master section & Slave section.
• Both sections are gated latch EXCEPT the slave section is
clocked on the inverted clock pulse and is controlled by
the outputs of the master section.

Chapter 2 Prepared by: Pn Siti Zura A. Jalil 47

 The truth table operation is SAME as that for edge-
triggered J-K flip-flop EXCEPT the way it is clocked.

Chapter 2 Prepared by: Pn Siti Zura A. Jalil 48

 Pulse-triggered (master-slave) J-K flip-flop logic
symbols
• Symbol ( ) at the output is the ANSI/IEEE postponed
output symbol.
• It mean that the output does not reflect the J-K input data
until the occurrence of of the clock edge (+ve or –ve)
following the triggering edge.

Chapter 2 Prepared by: Pn Siti Zura A. Jalil 49

 Flip-Flop Timing Considerations

• Important timing parameters:

– Setup and hold times
– Propagation delay – the time for a signal at the
input to be shown at the output.
– Maximum clocking frequency – highest clock
frequency that will give a reliable output.
– Clock pulse high and low times – minimum
time that clock must high before going low, and
low before gong high.
Chapter 2 Prepared by: Pn Siti Zura A. Jalil 50
 Setup and Hold Times
• Setup time, tS is the minimum time interval
before the active CLK transition that the
control input must be kept at the proper
level.
• Hold time, tH is the time following the active
transition of the CLK during which the
control input must kept at the proper level.

Chapter 2 Prepared by: Pn Siti Zura A. Jalil 51

 Control inputs must be held stable for
(a) a time tS prior to active clock transition and for
(b) a time tH after the active block transition.

Chapter 2 Prepared by: Pn Siti Zura A. Jalil 52

 FF propagation delays.

Chapter 2 Prepared by: Pn Siti Zura A. Jalil 53

 (a) Clock LOW and HIGH times;
(b) asynchronous pulse width.

Chapter 2 Prepared by: Pn Siti Zura A. Jalil 54

 Flip-Flop Applications
• Examples of applications:
– Counting
– Storing binary data
– Transferring binary data between locations
• Many FF applications are categorized as
sequential, which means that the output
follows a predetermined sequence of states.

Chapter 2 Prepared by: Pn Siti Zura A. Jalil 55