Logic and Computer Design Fundamentals
Chapter 3 – Combinational
Logic Design
Part 1 – Introduction and Encoder
Charles Kime & Thomas Kaminski
© 2004 Pearson Education, Inc.
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Overview
Part1 - Introduction
Design Topics
• Design hierarchy
Design Procedure
• The major design steps: specification, formulation,
optimization, technology mapping, and verification
Technology Mapping
• From AND, OR, and NOT to other gate types
• Decoders
Part 2
• Encoders
• Multiplexers
• Binary Adders
Chapter 3 - Part 1 2
Combinational Circuits
A combinational logic circuit has:
• A set of m Boolean inputs,
• A set of n Boolean outputs, and
• n switching functions, each mapping the 2m input
combinations to an output such that the current output
depends only on the current input values
A block diagram:
Combinatorial
Logic
Circuit
m Boolean Inputs n Boolean Outputs
Chapter 3 - Part 1 3
Hierarchical Design
To control the complexity of the function mapping inputs to
outputs:
• Decompose the function into smaller pieces called blocks
• Decompose each block’s function into smaller blocks, repeating as
necessary until all blocks are small enough
• Any block not decomposed is called a primitive block
• The collection of all blocks including the decomposed ones is a
hierarchy
Example: 9-input parity tree (see next slide)
• Top Level: 9 inputs, one output
• 2nd Level: Four 3-bit odd parity trees in two levels
• 3rd Level: Two 2-bit exclusive-OR functions
• Primitives: Four 2-input NAND gates
• Design requires 4 X 2 X 4 = 32 2-input NAND gates
Chapter 3 - Part 1 4
Hierarchy for Parity Tree Example
X0
X1
X2
X3 9-Input
X4 odd ZO
X5 function
X6 X0 A0
X7 3-Input
X8 X1 A1 odd BO
function
(a) Symbol for circuit X2 A2
X3 A0 A0
3-Input 3-Input
X4 A1 odd BO A1 odd B ZO
O
function function
X5 A2 A2
X6 A0
3-Input
X7 A1 odd BO
function
X8 A2
(b) Circuit as interconnected 3-input odd
function blocks
A0
A1 BO
A2
(c) 3-input odd function circuit as
interconnected exclusive-OR
blocks
(d) Exclusive-OR block as interconnected
NANDs
Chapter 3 - Part 1 5
Design Example
1. Specification
• BCD to Excess-3 code converter
• Transforms BCD code for the decimal digits to
Excess-3 code for the decimal digits
• BCD code words for digits 0 through 9: 4-bit
patterns 0000 to 1001, respectively
• Excess-3 code words for digits 0 through 9: 4-bit
patterns consisting of 3 (binary 0011) added to
each BCD code word
• Implementation:
multiple-level circuit
NAND gates (including inverters)
Chapter 3 - Part 1 6
Design Example (continued)
2. Formulation
• Conversion of 4-bit codes can be most easily
formulated by a truth table
• Variables Input BCD Output Excess-3
- BCD: ABCD WXYZ
A,B,C,D 0000 0011
• Variables 0001 0100
0010 0101
- Excess-3 0011 0110
W,X,Y,Z 0100 0111
• Don’t Cares 0101 1000
- BCD 1010 0110 1001
0111 1010
to 1111 1000 1011
1001 1011
Chapter 3 - Part 1 7
Design Example (continued)
C C
3. Optimization z 1 1
y 1 1
0 1 3 2 0 1 3 2
a. 2-level using 1
4 5 7
1
6
1
4 5
1
7 6
K-maps X X X X B X X X X B
12 13 15 14 12 13 15 14
W = A + BC + BD A 1
8 9
X
11
X
10
A 1
8 9
X
11
X
10
X = B C + B D + BC D
D D
Y = CD + CD
Z=D C C
x w
1 1 1
0 1 3 2 0 1 3 2
1 1 1 1
4 5 7 6 4 5 7 6
X X X X B X X X X B
12 13 15 14 12 13 15 14
A 8
1
9
X
11
X
10
A 1
8
1
9
X
11
X
10
D Chapter 3 - D
Part 1 8
Design Example (continued)
3. Optimization (continued)
b. Multiple-level using transformations
W = A + BC + BD
X = B C + B D + BCD
Y = CD + C D
Z=D G = 7 + 10 + 6 + 0 = 23
• Perform extraction, finding factor:
T1 = C + D
W = A + BT1
X = B T1 + B CD
Y = CD + C D
Z= D G = 2 + 1 + 4 + 7 + 6 + 0 = 19
Chapter 3 - Part 1 9
Design Example (continued)
3. Optimization (continued)
b. Multiple-level using transformations
T1 = C + D
W = A + BT1
X = B T1 + B CD
Y = CD + C D
Z =D G = 19
• An additional extraction not shown in the text since it
uses a Boolean transformation: ( CD = C + D = T1 ):
W = A + BT1
X = B T1 + B T1
T
Y = CD + 1
D
Z= G = 2 +1 + 4 + 6 + 4 + 0 = 16!
Chapter 3 - Part 1 10
Design Example (continued)
4. Technology Mapping
• Mapping with a library containing inverters and 2-input
NAND, 2-input NOR, and 2-2 AOI gates
A A
W
W
B X
B
X
C
C Y
D D Y
Z
Z
Chapter 3 - Part 1 11
Decoding
Decoding - the conversion of an n-bit input
code to an m-bit output code with
n £ m £ 2n such that each valid code word
produces a unique output code
Circuits that perform decoding are called
decoders
Here, functional blocks for decoding are
• called n-to-m line decoders, where m £ 2n, and
• generate 2n (or fewer) minterms for the n input
variables
Chapter 4 12
Decoder Examples
1-to-2-Line DecoderA D0 D1
D0 5 A
0 1 0
1 0 1 A D1 5 A
2-to-4-Line Decoder (a) (b)
A0
A1 A0 D0 D1 D2 D3
A1
0 0 1 0 0 0 D0 5 A 1 A 0
0 1 0 1 0 0
1 0 0 0 1 0
1 1 0 0 0 1 D1 5 A 1 A 0
(a)
D2 5 A 1 A 0
Note that the 2-4-line
made up of 2 1-to-2- D3 5 A 1 A 0
line decoders and 4 AND
(b)
gates. Chapter 4 13
Decoder with Enable
In general, attach m-enabling circuits to the outputs
See truth table below for function
• Note use of X’s to denote both 0 and 1
• Combination containing two X’s represent four binary combinations
Alternatively, can be viewed as distributing value of signal
EN to 1 of 4 outputs EN
A
In this case, called a
1
demultiplexer A 0
D 0
EN A 1 A 0 D0 D1 D2 D3 D1
0 X X 0 0 0 0
1 0 0 1 0 0 0 D2
1 0 1 0 1 0 0
1 1 0 0 0 1 0
D3
1 1 1 0 0 0
(b)
Chapter 4 14
2-to-4 Decoder Diagram
Chapter 3 - Part 1 15
NAND Only
D 0 E . A1 . A 0
D 1 E . A1 . A 0
D 2 E . A1 . A 0
D 0 E . A1 . A 0
Chapter 3 - Part 1 16
Decoder Expansion
General procedure given in book for any decoder with
n inputs and 2n outputs.
This procedure builds a decoder backward from the
outputs.
The output AND gates are driven by two decoders with
their numbers of inputs either equal or differing by 1.
These decoders are then designed using the same
procedure until 2-to-1-line decoders are reached.
The procedure can be modified to apply to decoders
with the number of outputs ≠ 2n
Chapter 4 17
3-to-8-line decoder (without enable)
Consider a 3-to-8-line decoder (without enabler)
A2 A1 A0 D0 D1 D2 D3 D4 D5 D6 D7
0 0 0 1
0 0 1 1
0 1 0 1
0 1 1 1
1 0 0 1
1 0 1 1
1 1 0 1
1 1 1 1
Chapter 4 18
3-to-8-line Decoder Implementation
Chapter 3 - Part 1 19
Easier way by Expansion
Decoder expansion
• Combine two or more small decoders with
enable inputs to form a larger decoder
3-to-8-line decoder constructed from two 2-to-
4-line decoders
The MSB is connected to the enable inputs
if A2=0, upper is enabled; if A2=1, lower is
enabled.
Chapter 3 - Part 1 20
Expansion
Chapter 3 - Part 1 21
Combinational Circuit Design with Decoders
Combinational circuit implementation with
decoders
• A decoder provide 2n minterms of n input
variables
• Since any Boolean function can be expressed
as a sum of minterms, one can use a decoder
and external OR gates to implement any
combinational function.
Chapter 3 - Part 1 22
Combinational Circuit Design with Decoders
Realize F (X,Y,Z) = Σ (1, 4, 7) with a decoder:
Chapter 3 - Part 1 23
Decoder Implementation of a Full Adder
Truth Table: We have two outputs, called S, which stands for
sum, and C, which stands for carry. Both sum and carry are
functions of X, Y, and Z.
Chapter 3 - Part 1 24
Decoder Implementation of a Full Adder
The output functions S & C can be expressed in sum-of-minterms
forms as follows:
S is implemented by taking minterms 1, 2, 4, and 7 and the OR
gates forms the logical sum of minterm for S
Similarly, carry C is implemented by taking logical sum of
minterms 3, 5, 6, and 7 from the same decoder
Chapter 3 - Part 1 25
