Title of the Course: COMPUTER ORGANIZATION AND ARCHITECTURE

Course Code:18EC35
Semester: 3rd ,B.E
Department: Electronics and Communication
Name and designation of the faculty:Mangala S Jolad,Asst Prof

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 MODULE 3
Input/Output
Organization

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ACCESSING I/O-DEVICES

A single bus-structure can be used for connecting I/O-devices to a computer

as shown in below Figure.
Each I/O device is assigned a unique set of address.
Bus consists of 3 sets of lines to carry address, data & control signals.
When processor places an address on address-lines, the intended-device
responds to the command.
The processor requests either a read or write-operation.
The requested-data are transferred over the data-lines.
There are 2 ways to deal with I/O-devices:
1) Memory-mapped I/O 2) I/O-mapped I/O.

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Memory-Mapped I/O

Memory and I/O-devices share a common address-space.

Any data-transfer instruction (like Move, Load) can be used to exchange information.
For example,
Move DATAIN, R0; This instruction sends the contents of location DATAIN to
register R0.
Here, DATAIN -> address of the input-buffer of the keyboard.
Move R0 ,DATAIN ; This instruction sends the contents register R0 to location
DATAIN.

I/O-Mapped I/O
Memory and I/0 address-spaces are different.
A special instructions named IN and OUT are used for data-transfer.
Advantage of separate I/O space: I/O-devices deal with fewer address-lines. 4
I/O Interface for an Input Device
Address Decoder: enables the device to recognize its address when this address
appears on the address-lines as shown in below Figure.
Status Register: contains information relevant to operation of I/O-device.
Data Register: holds data being transferred to or from processor. There are 2 types:
i)DATAIN -> Input-buffer associated with keyboard.
ii)DATAOUT -> Output data buffer of a display/printer

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MECHANISMS USED FOR INTERFACING I/O-DEVICES
Program Controlled I/O
Processor repeatedly checks status-flag to achieve required synchronization
between processor & I/O device. (We say that the processor polls the
device).
Main drawback: The processor wastes time in checking status of device before
actual data-transfer takes place.
Interrupt I/O
I/O-device initiates the action instead of the processor.
I/O-device sends an INTR signal over bus whenever it is ready for a data-
transfer operation.
Like this, required synchronization is done between processor & I/O device.

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Direct Memory Access (DMA)
Device-interface transfer data directly to/from the memory without
continuous involvement by the processor.
DMA is a technique used for high speed I/O-device.

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INTERRUPTS
In many situations where other tasks can be performed while waiting for an
I/O device to become ready.
A hardware signal called an Interrupt will alert the processor when an I/O
device becomes ready.
Interrupt-signal is sent on the interrupt-request line.
The processor can be performing its own task without the need to
continuously check the I/O-device.
The routine executed in response to an interrupt-request is called ISR.
The processor must inform the device that its request has been recognized
by sending INTA signal. (INTR à Interrupt Request, INTA à Interrupt
Acknowledge, ISR à Interrupt Service Routine)
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For example, consider COMPUTE and PRINT routines as shown in below Figure.
The processor first completes the execution of instruction i.
Then, processor loads the PC with the address of the first instruction of the ISR.
After the execution of ISR, the processor has to come back to instruction i+1.
Therefore, when an interrupt occurs, the current content of PC is put in temporary
storage location.
A return at the end of ISR reloads the PC from that temporary storage location.
This causes the execution to resume at instruction i+1.
When processor is handling interrupts, it must inform device that its request has been
recognized.

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This may be accomplished by INTA signal.
The task of saving and restoring the information can be done automatically
by the processor.
The processor saves only the contents of PC & Status register.
Saving registers also increases the Interrupt Latency.
Interrupt Latency is a delay between
→ time an interrupt-request is received and
→ start of the execution of the ISR.
Generally, the long interrupt latency in unacceptable.

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Difference between Subroutine & ISR

Subroutine ISR

A subroutine performs a function

required by the program from which ISR may not have anything in
it is called. common with program being
executed at time INTR is received.

Subroutine is just a linkage of 2 or Interrupt is a mechanism for

more function coordinating I/O transfer
related to each other.

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INTERRUPT HARDWARE
Most computers have several I/O devices that can request an interrupt.
A single interrupt-request (INTR) line may be used to serve n devices as shown below.
All devices are connected to IR line via switches to ground.
To request an interrupt, a device closes its associated switch.
Thus, if all IR signals are inactive, the voltage on the IR line will be equal to V dd.
When a device requests an interrupt, the voltage on the line drops to 0.
This causes the INTR received by the processor to go to 1.

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INTERRUPT HARDWARE CONTD…
The value of INTR is the logical OR of the requests from individual devices.
INTR=INTR1+ INTR2 +…….+INTRn
A special gate known as open-collector or open-drain are used to drive the INTR line.
The Output of the open collector control is equal to a switch to the ground that is
→ open when gates input is in ”0‟ state and
→ closed when the gates input is in “1‟ state.
Resistor R is called a Pull-up Resistor because it pulls the line voltage up to the high-
voltage state when the switches are open.

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ENABLING & DISABLING INTERRUPTS
All computers fundamentally should be able to enable and
disable interruptions as desired.
The problem of infinite loop occurs due to successive
interruptions of active INTR signals.
There are 3 mechanisms to solve problem of infinite loop:
 Processor should ignore the interrupts until execution of first
instruction of the ISR.
 Processor should automatically disable interrupts before
starting the execution of
the ISR.
 Processor has a special INTR line for the interrupt-handling
circuit.
Interrupt-circuit responds only to leading edge of signal. Such
line is called edge-triggered.
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Sequence of events involved in handling an interrupt-request:

1. The device raises an interrupt-request.

2. The processor interrupts the program currently being
executed.
3. Interrupts are disabled by changing the control bits in the
processor status register (PS).
4. The device is informed that its request has been recognized.
5. In response, the device deactivates the interrupt-request
signal.
6. The action requested by the interrupt is performed by the
interrupt-service routine.
7. Interrupts are enabled and execution of the interrupted
program is resumed.

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HANDLING MULTIPLE DEVICES
While handling multiple devices, the issues concerned are:
How can the processor recognize the device requesting an interrupt?
How can the processor obtain the starting address of the appropriate ISR?
Should a device be allowed to interrupt the processor while another
interrupt is being serviced?
How should 2 or more simultaneous interrupt-requests be handled?

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 POLLING
Information needed to determine whether device is requesting interrupt is available
in status-register
Following condition-codes are used:
DIRQ -> Interrupt-request for display.
KIRQ -> Interrupt-request for keyboard.
KEN -> keyboard enable.
DEN -> Display Enable.
SIN, SOUT -> status flags.
For an input device, SIN status flag in used.
SIN = 1 -> when a character is entered at the keyboard.
SIN = 0 -> when the character is read by processor.
IRQ=1 -> when a device raises an interrupt-requests as shown above.
Simplest way to identify interrupting-device is to have ISR poll all devices connected
to bus.
The first device encountered with its IRQ bit set is serviced.
After servicing first device, next requests may be serviced.

Advantage: Simple & easy to implement.

Disadvantage: More time spent polling IRQ bits of all devices.
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VECTORED INTERRUPTS
 To reduce the time of polling process , a device requesting an interrupt
identifies itself directly to the processor by sending a special-code to
processor over bus.
The term VECTORED INTERRUPTS refer to all interrupt handling schemes based on
this approach
Then, the processor starts executing the ISR.
The special-code indicates starting-address of ISR.
The special-code length ranges from 4 to 8 bits.
The location pointed to by the interrupting-device is used to store the
staring address to ISR.

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VECTORED INTERRUPTS CONTD……
The staring address to ISR is called the interrupt vector.
Processor → loads interrupt-vector into PC & executes appropriate ISR.
When processor is ready to receive interrupt-vector code , it activates INTA line.
I/O-devices send the interrupt-vector code over the data bus.
When a device sends an interrupt request, the processor may not be ready to receive
the interrupt-vector code immediately.
When the processor is ready to receive the interrupt vector code, it activates the
interrupt acknowledge line , INTA
Then, I/O-device responds by sending its interrupt-vector code & turning off the INTR
signal.
The interrupt vector also includes a new value for the Processor Status Register .

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CONTROLLING DEVICE REQUESTS
Following condition-codes are used:
KEN -> Keyboard Interrupt Enable.
DEN -> Display Interrupt Enable.
KIRQ/DIRQ -> Keyboard/Display unit requesting an interrupt.
There are 2 independent methods for controlling interrupt-requests. (IE -> interrupt-
enable).
At Device-end
IE bit in a control-register determines whether device is allowed to generate an
interrupt-request.
At Processor-end, interrupt-request is determined by
→ IE bit in the PS register or
→ Priority structure

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 INTERRUPT NESTING
A multiple-priority scheme is implemented by using separate INTR & INTA lines for
each device
Each INTR line is assigned a different priority-level as shown below.
Priority-level of processor is the priority of program that is currently being executed.
Processor accepts interrupts only from devices that have higher-priority than its own.
At the time of execution of ISR for some device, priority of processor is raised to that
of the device.
Thus, interrupts from devices at the same level of priority or lower are disabled.

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Privileged Instruction
Processor's priority is encoded in a few bits of PS word. (PS à Processor-Status).
Encoded-bits can be changed by Privileged Instructions that write into PS.
Privileged-instructions can be executed only while processor is running in Supervisor
Mode.
Processor is in supervisor-mode only when executing operating-system routines.
Privileged Exception
User program cannot
→ accidently or intentionally change the priority of the processor &
→ disrupt the system-operation.
An attempt to execute a privileged-instruction while in user-mode leads to a
Privileged Exception.

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 DIRECT MEMORY ACCESS (DMA)
The transfer of a block of data directly b/w an external device & main-
memory without continuous involvement by processor is called DMA.

DMA controller
→ is a control circuit that performs DMA transfers as shown below.
→ is a part of the I/O device interface.
→ performs the functions that would normally be carried out by processor.

While a DMA transfer is taking place, the processor can be used to execute
another program.

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 DMA interface has three registers as shown:
 First register is used for storing starting-address.
 Second register is used for storing word-count.
 Third register contains status- & control-flags.
The R/W bit determines direction of transfer.
If R/W=1, controller performs a read-operation (i.e. it transfers
data from memory to I/O), Otherwise, controller performs a
write-operation (i.e. it transfers data from I/O to memory).
If Done=1, the controller
→ has completed transferring a block of data and
→ is ready to receive another command. (IE à Interrupt
Enable).

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If IE=1, controller raises an interrupt after it has completed
transferring a block of data.
If IRQ=1, controller requests an interrupt.
Requests by DMA devices for using the bus are always given
higher priority than processor requests.

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There are 2 ways in which the DMA operation can be carried out:
Processor originates most memory-access cycles.
 DMA controller is said to "steal" memory cycles from processor.
 Hence, this technique is usually called Cycle Stealing.
DMA controller is given exclusive access to main-memory to transfer a block of data
without any interruption. This is known as Block Mode (or burst mode).

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