ARM Tachnology

1
Chapter 1

CORTEX M3

2
CONTENTS
 Objectives

 Introduction

 Cortex-M3 Processor

 Cortex M3 interrupt handling

 Cortex-M3 Memory Map

 Power Management

 System Timer (SysTick)

 Debug Capabilities

3
OBJECTIVES

 Familiarize with Cortex M3

 At the end of the part you will be able to List the

main features of the Cortex M3

4
CONTENTS
 Objectives

 Introduction

 Cortex-M3 Processor

 Cortex M3 interrupt handling

 Cortex-M3 Memory Map

 Power Management

 System Timer (SysTick)

 Debug Capabilities

5
What is ARM(Advanced Risc Machines)?

 ARM is an UK company that designs

innovative 32-bit microprocessors

 ARM leads the world of RISC

microprocessor cores

 ARM develops directly and through

partnership the tools, systems and
services to support its architecture.

6
Why use an ARM-based processor?
 Most popular 32-bit core
 Becoming an industrial standard like the C51

 Compatible leading edge core roadmap

 ARM7 -> ARM9 /10->CortexM3, M4,…

 Large number of product choices

 Multiple vendors means a large choice

7
Why use an ARM-based processor?
Sales in billions of dollars

8
Why Cortex M3?

9
Why Cortex M3?

More Than 28 company

ST, NXP, Atmel, Samsung…
Cortex-A Series, applications processors for complex OS and user applications.
Cortex-R Series, real-time systems profile.
Cortex-M Series, microcontroller profile optimized for cost-sensitive applications..
The number at the end of the Cortex name refers to the relative performance
level, with 1 the lowest and 8 the highest.

10
ARM Cortex-M code size advantage
explained

11
Industry standard

12
CONTENTS
 Objectives

 Introduction

 Cortex-M3 Processor

 Cortex M3 interrupt handling

 Cortex-M3 Memory Map

 Power Management

 System Timer (SysTick)

 Debug Capabilities

13
 Cortex-M3 Processor(1/2)
 Hierarchical processor integrating core and advanced
system peripherals

 Cortex-M3 Processor
 Cortex-M3 core
 Configurable interrupt controller
 Bus matrix
 Advanced debug components(ETM…)
 Optional MPU(Not available in STM32F10x)

 Cortex-M3 core
 Harvard architecture
 3-stage pipeline prediction
 Thumb®-2
 ALU w. H/W divide and single cycle multiply

14
Cortex-M3 Processor(2/2)
Non Maskable 3-Stage Pipeline, Harvard Architecture,
Interrupt Thumb-2 ISA (or Thumb) 30K* Gates

1-240 Configurable
Interrupts
with Configurable Priority
Levels

SWD or JTAG

Breakpoints

Data Watchpoints
& Trace

* Preliminary gate counts & power consumption based on initial implementation Cortex M3 Total
Gate Counts are based on TSMC 0.18 at 50MHz
60k* Gates
Optional ETM & MPU gate counts not included

15
Cortex-M3 Processor Main Features
 ARM v7M Architecture
 Thumb-2 Instruction Set Architecture
 Mix of 16 and 32 bit instructions for very high code density

 Harvard architecture
 Separate I & D buses allow parallel instruction fetching & data storage

 Integrated Nested Vectored Interrupt Controller (NVIC) Vector Table is

addresses.
 Integrated Bus Matrix
 Data memory management
 3 Stage Pipeline
 Integrated System Timer (SysTick) for Real Time OS

16
Data Memory management (1/7)

 Cortex-M3 includes two technologies to reduce Data memory requirements:

1. Unaligned Data Support
2. Atomic Bit Banding

 These technologies can dramatically improve data (SRAM) memory utilization, potentially
enabling silicon designers and users to reduce the amount of SRAM required and
dramatically impacting silicon usage.

17
 Data Memory management(2/7)
• Unaligned Data Support:
Other Core does not ARM Cortex-M3
support unaligned supports unaligned
data data that can improve
SRAM utilization
Long (32) Long (32)
Long (32) Long (32)
short (16) short (16) short (16)
short (16) Char Char Char Char
Data Char
aligned on Char
word
boundaries Char
Char

Unused (wasted) space Free space Can be used

Reduces SRAM Memory Requirements By Over

50%
Less Memory - LowER Cost
devices
18
Data Memory management(3/7)

long (32) Structure long (32)

management
char (8) char (8) long (32) …
example
long (32) … long char (8) char (8) char (8)
32bit machine
which does char (8) char (8) char (8) int (16) long (32) …
not support int (16)c
int (16) … long
unaligned data Data
aligned
long (32) char (8) int (16) long …

int (16)c char (8) … long (32)

int (16)

long (32)

Unused (wasted) space Free space for the rest of the application

Reduces SRAM Memory Requirements By Over

25%

19
 Data Memory management(4/7)
• Bit Banding:
 Traditional method  Speed and code size optimized
Cortex-M3 implementation
Disable external events

Read byte (RAM, register) 32bit

REAL
0 1 0 0 1 0 1 1 @Rbase+N b31 b0 memory
image
example: 20000000h to 200FFFFFh
Mask and modify bit element
X X X X X 1 X X
b31
VIRTUAL
Write byte (RAM, register) aliased
bit banding
0 1 0 0 1 1 1 1 image
b0
Enable external events
♦ Bit Banding done by bus matrix.
♦ Single instruction Read/Modify/Write (no more masking).
♦ No new instruction set  Use standard data one (AND, OR, XOR…).
Optimized RAM, peripherals and IOs registers accesses Easy multi-task
semaphore management

20
Data Memory management(5/7)
32MB alias region

1MB Peripheral bit-band region

21
 Data Memory management(6/7)
• Bit Banding formula is:

bit_word_addr = bit_band_base + (byte_offset x 32) + (bit_number × 4)

where:
bit_word_addr: is the address of the word in the alias memory region that
maps to the targeted bit.

bit_band_base is the starting address of the alias region (0x22000000 )

byte_offset is the number of the byte in the bit-band region that contains the
targeted bit

bit_number is the bit position of the targeted bit(0-7)

. Example -1:
How to map bit 2 of the byte located at Peripheral X address 0x20000300 in the
alias region (Peripheral X based address is 0x20000000 ):

22
Data Memory management(7/7)
• Solution:

0x22006008 = 0x22000000 + (0x300*32) + (2*4).

Writing to address 0x22006008 has the same effect as a read-modify-write

operation on bit 2 of the byte at SRAM address 0x20000300.
Reading address 0x22006008 returns the value (0x01 or 0x00) of bit 2 of the
byte at SRAM address 0x20000300 (0x01: bit set; 0x00: bit reset).

For more information on Bit-Banding, please refer to the Cortex™-M3

Technical Reference Manual.

23
 Instruction Pipeline(1/3)
 PC points to fetch stage:

Instruction fetched from memory

FETCH

Instruction decoded
DECODE

Register(s) read from Register Bank

EXECUTE Shift and ALU operation or memory access
Write register(s) back to Register Bank

24
 Instruction Pipeline(2/3)
 Optimal Pipelining:
Cycle 1 2 3 4 5 6 7 8 9
Operation
ADD F D E
SUB F D E
ORR F D E
AND F D E
ORR F D E
EOR F D E

F- Fetch D - Decode E - Execute

 All operations here are registers (single cycle execution)
 In this example it takes 6 cycles to execute 6 instructions
 Clock cycles per Instructions (CPI) = 1

25
 Instruction Pipeline(3/3)
 Flushing :
A flush of the pipeline can occur because of
 A Branch
 An exception
 A breakpoint

 Branch Pipeline Example:

Cycle 1 2 3 4 5 6 7 8 9
Address Operation
0x8000 B 0x8FEC F D E
0x8002 SUB F D
0x8004 ORR F
0x8FEC AND F D E
0x8FEE ORR F D E
0x8FF0 EOR F D E

F- Fetch D - Decode E - Execute

26
Register Set(1/2)
 Registers R0-R12 are simple registers that Register Set

can be used to hold program variables. R0

R1

 Registers R13-R15 have special functions R2

R3

within the Cortex CPU. R4

R5
 R13: Register R13 is used as the stack pointer R6
R7
 R14: called the link register. used to store the R8

return address when a call is made to a procedure R9

R10
 R15: is the program counter R11
R12
 xPSR:The Program Status Register contains R13(SP)
R14(LR)
status fields for instruction execution R15 (PC)
xPSR

27
CONTENTS
 Objectives

 Introduction

 Cortex-M3 Processor

 Cortex M3 interrupt handling

 Cortex-M3 Memory Map

 System Timer (SysTick)

 Debug Capabilities

28
Interrupt Handling

 The Cortex-M3 processor integrates an advanced

Nested Vectored Interrupt Controller (NVIC)

 The NVIC supports up to 240 dynamically reprioritizes

interrupts each with up to 256 levels of priority

 Supports advanced features for next generation real-time

applications:
 Tail-chaining of pending interrupts
 Interrupt Pre-emption
 Late Arrival

29
 Interrupt Response- Tail Chaining(1/3)
IRQ1
Highest
IRQ2
42 CYCLES

ARM7 PUSH ISR 1 POP PUSH ISR 2 POP

Interrupt handling in
assembler code 26 16 26 16
s
Tail-chaining cle
Cy
k
Cortex-M3 PUSH ISR 1 ISR 2 POP l oc
C
Interrupt handling in HW in
12 6 12 ng
a vi
6 CYCLES S
%
65

ARM7 Cortex-M3

• 26 cycles from IRQ1 to ISR1 entered • 12 cycles from IRQ1 to ISR1 entered
•Up to 42 cycles • 12 cycles
•42 cycles from ISR1 exit to ISR2 entry •6 cycles from ISR1 exit to ISR2 entry
•16 cycles to return from ISR2 •12 cycles to return from ISR2

30
 Interrupt Response – Preemption(2/3)

IRQ1
Highest

IRQ2

42 CYCLES

ARM7 ISR 1 POP PUSH 2 ISR 2 POP

16 26 16

Cortex-M3 ISR 1 POP ISR 2 POP

1- 6 12
12 7-18 CYCLES

31
 Interrupt Response – Late Arriving(3/3)
Less than 12 cycle

IRQ1
Highest
IRQ2

ARM7 PUSH PUSH ISR 1 POP ISR 2 POP

26 26 16 16

Cortex-M3 PUSH ISR 1 ISR 2 POP

6 12
Tail-
Chaining

32
 Interrupt Response – Lab
More than12 cycle

Highest

NMI

IRQ1

IRQ2

IRQ3

Less than12 cycle

PUSH PUSH NMI ISR 1 POP ISR 2 ISR 3 POP

ISR 2  Push for ISR1 begins

Starts
 Pre-empted by NMI Cortex-M3
 New instruction fetch in
parallel minimises time to NMI •Following NMI processor tail-chains into ISR1
•ISR2 Completed
•Pop only occurs on return to “Main”

33
NVIC Registers
 Each interrupt input has several registers to control it
 Enable/Disable Bit
 Enable or disable the interrupt
 Can be set, cleared or read
 Pending Bit
 If the pending bit is set, then the interrupt is pending
 A pending interrupt can only be taken (become active) if it is enabled and it
has sufficient priority to run
 Pending bit can be set, cleared or read
 Active Bit
 A bit is set if the interrupt is executing or “active-stacked”
 “Active-stacked” means the interrupt was executing, but was pre-empted
by another higher-priority interrupt
 Active register is normally read only
 Priority field
 priority management for each interrupt

34
Cortex-M3 Exception Types

Type of
No. Exception Type Priority Descriptions
Priority

1 Reset -3 (Highest) fixed Reset

2 NMI -2 fixed Non-Maskable Interrupt
3 Hard Fault -1 fixed Default fault if other hander not
implemented
4 MemManage Fault 0 settable MPU violation or access to illegal locations
5 Bus Fault 1 settable Fault if AHB interface receives error
6 Usage Fault 2 settable Exceptions due to program errors
7-10 Reserved N.A. N.A.
11 SVCall 3 settable System Service call
12 Debug Monitor 4 settable Break points, watch points, external debug
13 Reserved N.A. N.A.
14 PendSV 5 settable Pendable request for System Device
15 SYSTICK 6 settable System Tick Timer
16 Interrupt #0 7 settable External Interrupt #0
…… ………………….. ……………… settable …………………..
256 Interrupt#240 247 settable External Interrupt #240

35
CONTENTS
 Objectives

 Introduction

 Cortex-M3 Processor

 Cortex M3 interrupt handling

 Cortex-M3 Memory Map

 Power Management

 System Timer (SysTick)

 Debug Capabilities

36
Cortex-M3 Memory Map

37
CONTENTS
 Objectives

 Introduction

 Cortex-M3 Processor

 Cortex M3 interrupt handling

 Cortex-M3 Memory Map

 Power Management

 System Timer (SysTick)

 Debug Capabilities

38
Power Management
 8bit Microcontroller like power mode management
 SLEEP NOW
♦ “Wait for Interrupt” instructions to enter low power mode
No more dedicated control register settings sequence
♦ “Wait for Event” instructions to enter low power mode
No need of Interrupt to wake-up from sleep
Rapid resume from sleep
 SLEEP on EXIT
♦ Sleep request done in interrupt routine
♦ Low power mode entered on interrupt return
Very fast wakeup time
 DEEP SLEEP
♦ Long duration sleep
From product side: PLL can be stopped or shuts down the
power to digital parts of the system
Enables low power consumption
 Optimized RUN mode CORE power consumption

39
CONTENTS
 Objectives

 Introduction

 Cortex-M3 Processor

 Cortex M3 interrupt handling

 Cortex-M3 Memory Map

 Power Management

 System Timer (SysTick)

 Debug Capabilities

40
System Timer (SysTick)
 Flexible system timer

 24-bit self-reloading down counter with end of count interrupt

generation

 2 configurable Clock sources

 Suitable for Real Time OS or other scheduled tasks

In STM32F10x the SysTick clock can be: CPU clock or CPU clock/8
(provided externally by the Reset Clock Control )

41
CONTENTS
 Objectives
 Introduction
 What is ARM ?
 Why use an ARM-based processor?
 Cortex-M3 Processor
 Cortex-M3 Processor Main Features
 Data Memory
 Instruction Pipeline
 Write Buffer
 Privilege, Modes, Stacks and Register Set
 Cortex M3 interrupt handling
 Exception/Interrupt Handling,
 NVIC Registers
 Cortex-M3 Exception Types
 Vector Table
 Cortex-M3 Memory Map
 Power Management
 System Timer (SysTick)
 Debug Capabilities
42
Debug Capabilities
 Three solutions are possible :

More pins available

ETM

JTAG

SWD
for the application

 Joint Test Action Group easy flashed application debugging

♦ 8 hardware breakpoints

 Serial Wire Debug for targeted low bandwidth data trace

 Enhanced Thematic Mapper capability for better real time debugging

 ♦ Instruction trace only

43
 Performance Real time

5 reasons
to choose
Power
Cortex-M3 Optimized
Management Memory

Powerful
Debugging

44