COMPUTER ORGANIZATION AND DESIGN

RISC-V
2 ed. nd

The Hardware/Software Interface

Chapter 4
The Processor
Performance Issues
 Longest delay determines clock period
 Critical path: load instruction
 Instruction memory  register file  ALU 
data memory  register file
 Not feasible to vary period for different
instructions
 Violates design principle
 Making the common case fast
 We will improve performance by pipelining

Chapter 4 — The Processor — 2

 §4.6 An Overview of Pipelining
Pipelining Analogy
 Pipelined laundry: overlapping execution
 Parallelism improves performance

 Four loads:
 Speedup
= 8/3.5 = 2.3
 Non-stop:
 Speedup
= 2n/0.5n + 1.5 ≈ 4
= number of stages

Chapter 4 — The Processor — 3

RISC-V Pipeline
 Five stages, one step per stage
1. IF: Instruction fetch from memory
2. ID: Instruction decode & register read
3. EX: Execute operation or calculate address
4. MEM: Access memory operand
5. WB: Write result back to register

Chapter 4 — The Processor — 4

 Pipeline Performance
 Assume time for stages is
 100ps for register read or write
 200ps for other stages
 Compare pipelined datapath with single-cycle
datapath

Instr Instr fetch Register ALU op Memory Register Total time

read access write
ld 200ps 100 ps 200ps 200ps 100 ps 800ps
sd 200ps 100 ps 200ps 200ps 700ps
R-format 200ps 100 ps 200ps 100 ps 600ps
beq 200ps 100 ps 200ps 500ps

Chapter 4 — The Processor — 5

Pipeline Performance
Single-cycle (Tc= 800ps)

Pipelined (Tc= 200ps)

Chapter 4 — The Processor — 6

Pipeline Speedup
 If all stages are balanced
 i.e., all take the same time
 Time between instructionspipelined
= Time between instructionsnonpipelined
Number of stages
 If not balanced, speedup is less
 Speedup due to increased throughput
 Latency (time for each instruction) does not
decrease

Chapter 4 — The Processor — 7

Pipelining and ISA Design
 RISC-V ISA designed for pipelining
 All instructions are 32-bits

Easier to fetch and decode in one cycle

c.f. x86: 1- to 17-byte instructions
 Few and regular instruction formats

Can decode and read registers in one step
 Load/store addressing

Can calculate address in 3rd stage, access memory
in 4th stage

Chapter 4 — The Processor — 8

Hazards
 Situations that prevent starting the next
instruction in the next cycle
 Structure hazards
 A required resource is busy
 Data hazard
 Need to wait for previous instruction to
complete its data read/write
 Control hazard
 Deciding on control action depends on
previous instruction

Chapter 4 — The Processor — 9

Structural Hazards
 Conflict for use of a resource
 In RISC-V pipeline with a single memory
 Load/store requires data access
 Instruction fetch would have to stall for that
cycle

Would cause a pipeline “bubble”
 Hence, pipelined datapaths require
separate instruction/data memories
 Or separate instruction/data caches

Chapter 4 — The Processor — 10

Data Hazards
 An instruction depends on completion of
data access by a previous instruction
 add x19, x0, x1
sub x2, x19, x3

Chapter 4 — The Processor — 11

Forwarding (aka Bypassing)
 Use result when it is computed
 Don’t wait for it to be stored in a register
 Requires extra connections in the datapath

Chapter 4 — The Processor — 12

Load-Use Data Hazard
 Can’t always avoid stalls by forwarding
 If value not computed when needed
 Can’t forward backward in time!

Chapter 4 — The Processor — 13

 Code Scheduling to Avoid Stalls
 Reorder code to avoid use of load result in
the next instruction
 C code for a = b + e; c = b + f;

ld x1, 0(x0) ld x1, 0(x0)

ld x2, 8(x0) ld x2, 8(x0)
stall
add x3, x1, x2 ld x4, 16(x0)
sd x3, 24(x0) add x3, x1, x2
ld x4, 16(x0) sd x3, 24(x0)
add x5, x1, x4 add x5, x1, x4
stall
sd x5, 32(x0) sd x5, 32(x0)
13 cycles 11 cycles

Chapter 4 — The Processor — 14

Control Hazards
 Branch determines flow of control
 Fetching next instruction depends on branch
outcome
 Pipeline can’t always fetch correct instruction

Still working on ID stage of branch
 In RISC-V pipeline
 Need to compare registers and compute
target early in the pipeline
 Add hardware to do it in ID stage

Chapter 4 — The Processor — 15

Stall on Branch
 Wait until branch outcome determined
before fetching next instruction

Chapter 4 — The Processor — 16

Branch Prediction
 Longer pipelines can’t readily determine
branch outcome early
 Stall penalty becomes unacceptable
 Predict outcome of branch
 Only stall if prediction is wrong
 In RISC-V pipeline
 Can predict branches not taken
 Fetch instruction after branch, with no delay

Chapter 4 — The Processor — 17

More-Realistic Branch Prediction
 Static branch prediction
 Based on typical branch behavior
 Example: loop and if-statement branches

Predict backward branches taken

Predict forward branches not taken
 Dynamic branch prediction
 Hardware measures actual branch behavior

e.g., record recent history of each branch
 Assume future behavior will continue the trend

When wrong, stall while re-fetching, and update history

Chapter 4 — The Processor — 18

Pipeline Summary
The BIG Picture
 Pipelining improves performance by
increasing instruction throughput
 Executes multiple instructions in parallel
 Each instruction has the same latency
 Subject to hazards
 Structure, data, control
 Instruction set design affects complexity of
pipeline implementation
Chapter 4 — The Processor — 19
 §4.7 Pipelined Datapath and Control
RISC-V Pipelined Datapath

MEM

Right-to-left WB
flow leads to
hazards

Chapter 4 — The Processor — 20

Pipeline registers
 Need registers between stages
 To hold information produced in previous cycle

Chapter 4 — The Processor — 21

Pipeline Operation
 Cycle-by-cycle flow of instructions through
the pipelined datapath
 “Single-clock-cycle” pipeline diagram

Shows pipeline usage in a single cycle

Highlight resources used
 c.f. “multi-clock-cycle” diagram

Graph of operation over time
 We’ll look at “single-clock-cycle” diagrams
for load & store

Chapter 4 — The Processor — 22

IF for Load, Store, …

Chapter 4 — The Processor — 23

ID for Load, Store, …

Chapter 4 — The Processor — 24

EX for Load

Chapter 4 — The Processor — 25

MEM for Load

Chapter 4 — The Processor — 26

WB for Load

Wrong
register
number

Chapter 4 — The Processor — 27

Corrected Datapath for Load

Chapter 4 — The Processor — 28

EX for Store

Chapter 4 — The Processor — 29

MEM for Store

Chapter 4 — The Processor — 30

WB for Store

Chapter 4 — The Processor — 31

Multi-Cycle Pipeline Diagram
 Form showing resource usage

Chapter 4 — The Processor — 32

Multi-Cycle Pipeline Diagram
 Traditional form

Chapter 4 — The Processor — 33

Single-Cycle Pipeline Diagram
 State of pipeline in a given cycle

Chapter 4 — The Processor — 34

Pipelined Control (Simplified)

Chapter 4 — The Processor — 35

Pipelined Control
 Control signals derived from instruction
 As in single-cycle implementation

Chapter 4 — The Processor — 36

Pipelined Control

Chapter 4 — The Processor — 37

 §4.8 Data Hazards: Forwarding vs. Stalling
Data Hazards in ALU Instructions
 Consider this sequence:
sub x2, x1,x3
and x12,x2,x5
or x13,x6,x2
add x14,x2,x2
sd x15,100(x2)

 We can resolve hazards with forwarding

 How do we detect when to forward?

Chapter 4 — The Processor — 38

Dependencies & Forwarding

Chapter 4 — The Processor — 39

Dependencies & Forwarding

Chapter 4 — The Processor — 40

Detecting the Need to Forward
 Pass register numbers along pipeline
 e.g., ID/EX.RegisterRs1 = register number for Rs1
sitting in ID/EX pipeline register
 ALU operand register numbers in EX stage
are given by
 ID/EX.RegisterRs1, ID/EX.RegisterRs2
 Data hazards when
Fwd from
1a. EX/[Link] = ID/EX.RegisterRs1 EX/MEM
1b. EX/[Link] = ID/EX.RegisterRs2 pipeline reg

2a. MEM/[Link] = ID/EX.RegisterRs1 Fwd from

2b. MEM/[Link] = ID/EX.RegisterRs2 MEM/WB
pipeline reg

Chapter 4 — The Processor — 41

Detecting the Need to Forward
 But only if forwarding instruction will write
to a register!
 EX/[Link], MEM/[Link]
 And only if Rd for that instruction is not x0
 EX/[Link] ≠ 0,
MEM/[Link] ≠ 0

Chapter 4 — The Processor — 42

Forwarding Paths

Chapter 4 — The Processor — 43

 Forwarding Conditions
Mux control Source Explanation
ForwardA = 00 ID/EX The first ALU operand comes from the register file.
ForwardA = 10 EX/MEM The first ALU operand is forwarded from the prior
ALU result.
ForwardA = 01 MEM/WB The first ALU operand is forwarded from data
memory or an earlier ALU result.

ForwardB = 00 ID/EX The second ALU operand comes from the register
file.
ForwardB = 10 EX/MEM The second ALU operand is forwarded from the prior
ALU result.
ForwardB = 01 MEM/WB The second ALU operand is forwarded from data
memory or an earlier ALU result.

Chapter 4 — The Processor — 44

Double Data Hazard
 Consider the sequence:
add x1,x1,x2
add x1,x1,x3
add x1,x1,x4
 Both hazards occur
 Want to use the most recent
 Revise MEM hazard condition
 Only fwd if EX hazard condition isn’t true

Chapter 4 — The Processor — 45

Revised Forwarding Condition
 MEM hazard
 if (MEM/[Link]
and (MEM/[Link] ≠ 0)
and not(EX/[Link] and (EX/[Link] ≠ 0)
and (EX/[Link] ≠ ID/EX.RegisterRs1))
and (MEM/[Link] = ID/EX.RegisterRs1)) ForwardA = 01
 if (MEM/[Link]
and (MEM/[Link] ≠ 0)
and not(EX/[Link] and (EX/[Link] ≠ 0)
and (EX/[Link] ≠ ID/EX.RegisterRs2))
and (MEM/[Link] = ID/EX.RegisterRs2)) ForwardB = 01

Chapter 4 — The Processor — 46

Datapath with Forwarding

Chapter 4 — The Processor — 47

Load-Use Hazard Detection
 Check when using instruction is decoded
in ID stage
 ALU operand register numbers in ID stage
are given by
 IF/ID.RegisterRs1, IF/ID.RegisterRs2
 Load-use hazard when
 ID/[Link] and
((ID/[Link] = IF/ID.RegisterRs1) or
(ID/[Link] = IF/ID.RegisterRs1))
 If detected, stall and insert bubble

Chapter 4 — The Processor — 48

How to Stall the Pipeline
 Force control values in ID/EX register
to 0
 EX, MEM and WB do nop (no-operation)
 Prevent update of PC and IF/ID register
 Using instruction is decoded again
 Following instruction is fetched again
 1-cycle stall allows MEM to read data for ld

Can subsequently forward to EX stage

Chapter 4 — The Processor — 49

Load-Use Data Hazard

Stall inserted
here

Chapter 4 — The Processor — 50

Datapath with Hazard Detection

MEM/[Link]

EX/[Link]

MEM/[Link]

Chapter 4 — The Processor — 51

Stalls and Performance
The BIG Picture
 Stalls reduce performance
 But are required to get correct results
 Compiler can arrange code to avoid
hazards and stalls
 Requires knowledge of the pipeline structure

Chapter 4 — The Processor — 52

 §4.9 Control Hazards
Branch Hazards
 If branch outcome determined in MEM

Flush these
instructions
(Set control
values to 0)

PC

Chapter 4 — The Processor — 53

Reducing Branch Delay
 Move hardware to determine outcome to ID
stage
 Target address adder
 Register comparator
 Example: branch taken
36: sub x10, x4, x8
40: beq x1, x3, 16 // PC-relative branch
// to 40+16*2=72
44: and x12, x2, x5
48: orr x13, x2, x6
52: add x14, x4, x2
56: sub x15, x6, x7
...
72: ld x4, 50(x7)

Chapter 4 — The Processor — 54

Example: Branch Taken

Chapter 4 — The Processor — 55

Example: Branch Taken

Chapter 4 — The Processor — 56

Data Hazards for Branches
 If a comparison register is a destination of
2nd or 3rd preceding ALU instruction

add x1, x2, x3 IF ID EX MEM WB

add x4, x5, x6 IF ID EX MEM WB

… IF ID EX MEM WB

beq x1, x4, target IF ID EX MEM WB

 Can resolve using forwarding

Chapter 4 — The Processor — 57

Data Hazards for Branches
 If a comparison register is a destination of
preceding ALU instruction or 2nd preceding
load instruction
 Need 1 stall cycle

lw x1, addr IF ID EX MEM WB

add x4, $x5, $x6 IF ID EX MEM WB

beq stalled IF ID

beq x1, x4, target ID EX MEM WB

Chapter 4 — The Processor — 58

Data Hazards for Branches
 If a comparison register is a destination of
immediately preceding load instruction
 Need 2 stall cycles

lw x1, addr IF ID EX MEM WB

beq stalled IF ID

beq stalled ID

beq x1, x0, target ID EX MEM WB

Chapter 4 — The Processor — 59