Computer Organization and

Architecture

CSE, 2/4 [Link] 1 sem

Credits: 3
Continuous Internal Evaluation : 30
Semester End Evaluation: 70
Total Marks: 100

Prerequisites: Introduction to Computers

Digital Logic Design
 Computer Organization and Architecture
UNIT-1
Register Transfer and Micro-Operations: Register Transfer Language, Register Transfer,
memory Transfers, Bus construction with Multiplexers, Arithmetic Micro-operations, Logic
Micro-operations, Shift Micro-operations, Arithmetic Logic Shift Unit.
UNIT-2
Basic Computer Organization: Instruction codes, Computer Registers, Computer Instructions,
Timing and Control, Instruction Cycle, Memory-Reference Instructions, Input- Output and
Interrupt.
UNIT-3
Central Processing Unit: General registers Organization, Stack Organization, Instruction
Formats, Addressing Modes, Data Transfer and Manipulation, Program Control
UNIT-4
Computer Arithmetic: Introduction, Addition and Subtraction, Booth Multiplication Algorithm.
Memory Organization: Memory Hierarchy, Main Memory, Auxiliary memory, Associative
Memory, Cache Memory, Virtual Memory.
UNIT-5
Input-Output Organization: Peripheral Devices, Input-output Interface, Asynchronous Data
Transfer, Priority Interrupt, Direct Memory Access (DMA), Input-Output Processor.
Pipeline and Parallel Processing: Parallel processing, Pipelining, Arithmetic pipeline,
Instruction pipeline.
 Course Outcomes
CO1: Understand the basic functional units of a
computer system and its organization (L2)

CO2: Apply appropriate instructions for processing

various types of computer operations (L3).

CO3: Apply various types of organizations on

registers (L3).

CO4: Analyze memory hierarchy, I/O

communication and pipelining (L4).

L1-remembering, L2-understanding, L3-applying, L4-analyzing, L5-evaluating, and L6-creating.

UNIT-3 CENTRAL PROCESSING UNIT

 General Register Organization

 Stack Organization
 Instruction Formats
 Addressing Modes
 Data Transfer and Manipulation
 Program Control

4
 MAJOR COMPONENTS OF CPU
Performs the bulk of data-processing
operations is called the central processing
unit and is referred to as the CPU.
Storage Components: The register set
stores intermediate data used during the
execution of the instructions.
Registers
Flip-flops

Execution (Processing) Components:

Arithmetic Logic Unit (ALU):
Arithmetic calculations,
Logical computations,
Shifts/Rotates
Register
Set ALU
Transfer Components:
Bus

Control Components:
Control Unit
The control unit supervises the transfer of Control Unit
information among the registers and 5
instructs the ALU as to which operation to
perform.
GENERAL REGISTER ORGANIZATION

Clock Input

R1
R2
R3
R4
R5
R6
R7
Load
(7 lines) SELA { MUX MUX } SELB
3x8 A bus B bus
decoder

SELD
OPR ALU

Output
3 3 3 5
Control Word SELA SELB SELD OPR 6
 OPERATION OF CONTROL UNIT
The control unit directs the information flow through ALU by:
- Selecting various Components in the system
- Selecting the Function of ALU
Example: R1 <- R2 + R3
[1] MUX A selector (SELA): BUS A  R2 to place the content of R2 into bus A .
[2] MUX B selector (SELB): BUS B  R3 to place the content o f R 3 into bus B .
[3] ALU operation selector (OPR): ALU to ADDto provide the arithmetic addition A + B .
[4] Decoder destination selector (SELD): R1  Out Bus to transfer the content
o f the output bus into
3 3 3 5 R1.
Control Word SELA SELB SELD OPR

Encoding of register selection fields

Binary
Code SELA SELB SELD
000 Input Input None
001 R1 R1 R1
010 R2 R2 R2
011 R3 R3 R3
100 R4 R4 R4
101 R5 R5 R5
110 R6 R6 R6
111 R7 R7 R7
7
 Control

ALU CONTROL
OPR
Encoding of ALU operations Select Operation Symbol
00000 Transfer A TSFA
00001 Increment A INCA
00010 ADD A + B ADD
00101 Subtract A - B SUB
00110 Decrement A DECA
01000 AND A and B AND
01010 OR A and B OR
01100 XOR A and B XOR
01110 Complement A COMA
10000 Shift right A SHRA
11000 Shift left A SHLA

Examples of ALU Microoperations

Symbolic Designation
Microoperation SELA SELB SELD OPR Control Word
R1  R2 - R3 R2 R3 R1 SUB 010 011 001 00101
R4  R4  R5 R4 R5 R4 OR 100 101 100 01010
R6  R6 + 1 R6 - R6 INCA 110 000 110 00001
R7  R1 R1 - R7 TSFA 001 000 111 00000
Output  R2 R2 - None TSFA 010 000 000 00000
Output  Input Input - None TSFA 000 000 000 00000
R4  shl R4 R4 - R4 SHLA 100 000 100 11000
R5  0 R5 R5 R5 XOR 101 101 101 01100
8
 Stack Organization
• Register Stack
• Memory Stack
• Reverse Polish Notation
• Evaluation of Arithmetic Expressions

9
 REGISTER STACK ORGANIZATION
Stack
- Very useful feature for nested subroutines, nested loops control
- Also efficient for arithmetic expression evaluation
- Storage which can be accessed in LIFO
- Pointer: SP
- Only PUSH and POP operations are applicable
stack Address

Register Stack Flags 63

FULL EMPTY

Stack pointer 4
SP C 3
B 2
A 1
Push, Pop operations 0
DR
/* Initially, SP = 0, EMPTY = 1, FULL = 0 */

PUSH POP
SP  SP + 1 DR  M[SP]
M[SP]  DR SP  SP - 1
If (SP = 0) then (FULL  1) If (SP = 0) then (EMPTY  1)
EMPTY  0 FULL  0 10
 MEMORY STACK ORGANIZATION
1000
Program
Memory with Program, Data, PC (instructions)
and Stack Segments
Data
AR (operands)

SP 3000
stack
3997
3998
3999
4000
- A portion of memory is used as a stack with a 4001
processor register as a stack pointer DR

- PUSH: SP  SP - 1
M[SP]  DR

- POP: DR  M[SP]
SP  SP + 1

- Most computers do not provide hardware to check

stack overflow (full stack) or underflow(empty stack) 11
 REVERSE POLISH NOTATION
Arithmetic Expressions: A + B
A+B Infix notation
+AB Prefix or Polish notation
AB+ Postfix or reverse Polish notation
- The reverse Polish notation is very suitable for stack
manipulation

Evaluation of Arithmetic Expressions

Any arithmetic expression can be expressed in parenthesis-free
Polish notation, including reverse Polish notation

(3 * 4) + (5 * 6)  34*56*+

6
4 5 5 30
3 3 12 12 12 12 42
3 4 * 5 6 * +

12
 Worksheet-1
1.

2.

3.

13
 Worksheet-1-Answers
1.

2.

3.

14
Worksheet-2

15
1.

2.

3.

4.

16
 Instruction Format

INSTRUCTION FORMAT
Instruction Fields
OP-code field - specifies the operation to be performed
Address field - designates memory address(s) or a processor register(s)
Mode field - specifies the way the operand or the
effective address is determined 1. ZERO-ADDRESS INSTRUCTIONS
2. ONE-ADDRESS INSTRUCTIONS
The number of address fields in the instruction format 3. TWO-ADDRESS INSTRUCTIONS
4. THREE-ADDRESS INSTRUCTIONS
depends on the internal organization of CPU

- The three most common CPU organizations:

Single accumulator organization:
ADD X /* AC  AC + M[X] */
General register organization:
ADD R1, R2, R3 /* R1  R2 + R3 */
ADD R1, R2 /* R1  R1 + R2 */
MOV R1, R2 /* R1  R2 */
ADD R1, X /* R1  R1 + M[X] */
Stack organization:
PUSH X /* TOS  M[X] */
ADD
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THREE, and TWO-ADDRESS INSTRUCTIONS
Three-Address Instructions:

Program to evaluate X = (A + B) * (C + D) :
ADD R1, A, B /* R1  M[A] + M[B]*/
ADD R2, C, D /* R2  M[C] + M[D] */
MUL X, R1, R2 /* M[X]  R1 * R2 */

- Results in short programs

- Instruction becomes long (many bits)

Two-Address Instructions:
Program to evaluate X = (A + B) * (C + D) :

MOV R1, A /* R1  M[A] */

ADD R1, B /* R1  R1 + M[B] */
MOV R2, C /* R2  M[C] */
ADD R2, D /* R2  R2 + M[D] */
MUL R1, R2 /* R1  R1 * R2 */
MOV X, R1 /* M[X]  R1 */
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ONE, and ZERO-ADDRESS INSTRUCTIONS
One-Address Instructions:
- Use an implied AC register for all data manipulation
- Program to evaluate X = (A + B) * (C + D) :
LOAD A /* AC  M[A] */
ADD B /* AC  AC + M[B] */
STORE T /* M[T]  AC */
LOAD C /* AC  M[C] */
ADD D /* AC  AC + M[D] */
MUL T /* AC  AC * M[T] */
STORE X /* M[X]  AC */
Zero-Address Instructions:
- Can be found in a stack-organized computer
- Program to evaluate X = (A + B) * (C + D) :
PUSH A /* TOS  A */
PUSH B /* TOS  B */
ADD /* TOS  (A + B) */
PUSH C /* TOS  C */
PUSH D /* TOS  D */
ADD /* TOS  (C + D) */
MUL /* TOS  (C + D) * (A + B) */
POP X /* M[X]  TOS */
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 Worksheet-3
1.

2.

20
Given:

Instruction Size=32 bit

Operand Size=12 bit

Instruction Format for 2 Address Instruction:

Number of 2 address instructions possible= 2^8=256

Number of 2 Address instructions available= 250

256–250=6 two Address instructions are free which can be used indicate the
given instruction is a 1 Address instruction.

So number of 1-Address instruction= 6*2^12=24576.

The above problem has been solved using
Expanding Opcode technique (i.e. length
21 of
opcode is not fixed).
cpe 252: Computer Organization 22
 Addressing Modes
• Microprocessor executes the instructions stored in
memory (RAM).
• It executes one instruction at a time.
• Each of the instruction contains operations and
operands.
• Operation specifies the type of action to be performed.
• For example: ADD, SUB, MOV, INC, LOAD, STORE
• Operands are the data on which the operation is to be
performed.
• MOV B, A Here MOV is operation and (B & A) are
operands.
• ADD B Here ADD is operation and (B) is operand.
cpe 252: Computer Organization 23
• Operand can be place either in one of the
processor registeror in memory.
• There are different ways to get the operands.
• The way in which the operand is taken from
register or memory is named as addressing
mode.

cpe 252: Computer Organization 24

 ADDRESSING MODES
 Specifies a rule for interpreting or modifying the address field of the
instruction (before the operand is actually referenced)
 The different ways of specifying the location of an operand in an
instruction are called as addressing modes
 Variety of addressing modes
- to give programming flexibility to the user
- to use the bits in the address field of the instruction efficiently
Types of addressing Modes:
1. Implied Mode
2. Immediate Mode
3. Register Mode
4. Register Indirect Mode
5. Auto-increment or Auto-decrement
6. Direct Address Mode
7. Indirect Addressing Mode
8. Relative Addressing Modes
9. Indexed Addressing Mode
[Link] Register Addressing Mode
[Link] addressing 25
 1. Implied Mode
• Address of the operands are specified implicitly in the
definition of the instruction
– No need to specify address in the instruction
– Opcode specifies the address of the operands
– EA = AC, or EA = Stack[SP], EA: Effective Address.

Examples :
CMA ( A A’ )
RAL
 2. Immediate Addressing
• Operand is part of instruction
• Operand = address field, No need to specify address in the
instruction
• e.g. ADD 5
– Add 5 to contents of accumulator
– 5 is operand
• No memory reference to fetch data
• Fast to acquire an operand
• Limited range
The instruction having ‘I’
(Immediate) letter fall under this
category
Examples :
MVI C,25H
MVI M,7CH
LXI D,245EH
 3. Register Addressing
Address specified in the instruction is the register address
• Data transfer between -Designated operand need to be in a register
- Shorter address than the memory address
Registers - Saving address field in the instruction
• Operand is held in register - Faster to acquire an operand than the memory addressing
- EA = IR(R) (IR(R): Register field of IR)
named in address filed
• EA = R
• Limited number of registers
• Very small address field needed
– Shorter instructions
– Faster instruction fetch
• No memory access
• Very fast execution
• Very limited address space
• Multiple registers helps
performance
– Requires good assembly
programming or compiler
writing
– N.B. C programming Examples :
• register int a; MOV A, R1
ADD A
 [Link] Indirect Addressing

• Instruction specifies a register which contains the memory address of the operand
– Saving instruction bits since register address is shorter than the memory address
– Slower to acquire an operand than both the register addressing or memory
addressing
– EA = [IR(R)] ([x]: Content of x)
• EA = (R)
• Operand is in memory cell pointed to by contents of register R
• Large address space (2n)
• One fewer memory access than indirect addressing
 5. Auto-increment or Auto-decrement
• A special case of indirect register mode
• The register whose number is included in the instruction code, contains
the address of the operand.
• When the address in the register is used to access memory, the value
in the register is incremented or decremented by 1 (after or before the
execution of the instruction), PC
• Autoincrement Mode = after operand addressing , the contents of
the register is incremented.
• Example : The register R4, the autoincrement mode is written as
(R4)+.
• Decrement Mode = before operand addressing, the contents of the
register is decrement.
• Example : The register R4, the autodecrement mode is written as
30
-
(R4).
 6. Direct Address Mode

 Instruction specifies the memory address which can be used directly

to the physical memory
 Faster than the other memory addressing modes
 Too many bits are needed to specify the address for a large physical
memory space
 EA = IR(address), (IR(address): address field of IR), Effective address
(EA) = address field (A)
 Single memory reference to access data
 No additional calculations to work out effective address
31
 Limited address space
 7. Indirect Addressing Mode

 Memory cell pointed to by address field contains the address of (pointer to) the
operand
 The address field of an instruction specifies the address of a memory location
that contains the address of the operand
 When the abbreviated address is used, large physical memory can be addressed
with a relatively small number of bits
 Slow to acquire an operand because of an additional memory access
 EA = M[IR(address)]
 Large address space
 2n where n = word length
 May be nested, multilevel, cascaded
 e.g. EA = (((A)))
 Draw the diagram yourself
 Multiple memory accesses to find operand 32
 Hence slower
 EA = Displacement + CPU
Register

EA = A + (R), In this the address field holds

two values, A (which is the base value) and
R (that holds the displacement), or vice
versa.

33
 8. Relative Addressing Modes
 A version of displacement addressing
 EA = A + (R), R = Program counter, PC, A = base value
 EA = A + (PC), i.e. get operand from A cells from current location
pointed to by PC c.f locality of reference & cache usage
 The Address fields of an instruction specifies the part of the address
PC Relative Addressing Mode (R = PC)
- EA = PC + IR (address)
- Address field of the instruction is short.
- Large physical memory can be accessed with a small number of
address bits.
- Advantage
- The relative addressing mode doesn’t require memory references.
- Disadvantage
34
- The relative addressing mode doesn’t have any disadvantages as
 9. Indexed Addressing Mode
• The index addressing mode is pretty helpful whenever the instructions in a
program access an array or large ranges of memory addresses.
• The effective address, in such a mode, is generated when we add a constant
to the content of the register. The register content does not ever change.
• Example:
XR: Index Register:
EA = XR + IR(address)
- Advantage
- Using the index addressing mode, we get flexibility for specifying
several locations of the memory.
- Disadvantage
- It is very complex to implement the index addressing mode.
35
 10. Base Register Addressing Mode
 A holds displacement
 R holds pointer to base address
 R may be explicit or implicit
 e.g. segment registers in 80x86
BAR: Base Address Register:
- EA = BAR + IR(address)

36
 11. Stack Addressing
Operand is (implicitly) on top of stack
e.g.
ADD Pop top two items from stack and add

37
 Worksheet-4
Address Memory
200 Load to AC Mode
LOAD A PC = 200 201 Address = 500
What is the content of A and 202 Next instruction
R1 = 400
EA of the following addressing
modes XR = 100
399 450
400 700

AC
500 800

600 900

Addressing Effective Content 702 325

Mode Address of AC
Direct address 500 /* AC  (500) */ 800
Immediate operand 800 300
Indirect address
Register
Register indirect
Autoincrement
Autodecrement
Relative address
Indexed address 38
 Worksheet-4 Answer
Address Memory
200 Load to AC Mode
PC = 200 201 Address = 500
202 Next instruction
R1 = 400

399 450
XR = 100
400 700

AC
500 800

600 900
Addressing Effective Content
Mode Address of AC
Direct address 500 /* AC  (500) */ 800 702 325
Immediate operand - /* AC  500 */ 500
Indirect address 800 /* AC  ((500)) */ 300
Register - /* AC  R1 */ 400 800 300
Register indirect 400 /* AC  (R1) */ 700
Autoincrement 400 /* AC  (R1)+ */ 700
Autodecrement 399 /* AC  -(R) */ 450
Relative address 702 /* AC  (PC+500) */ 325
Indexed address 600 /* AC  (XR+500) */ 900

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 Instructions Set
Data Transfer Instructions
Data Manipulation Instructions
Arithmetic Instructions
Logical and Bit Manipulation Instructions
Shift Instructions
Program Control Instructions
 DATA TRANSFER INSTRUCTIONS
Typical Data Transfer Instructions
Name Mnemonic
Load LD
Store ST
Move MOV
Exchange XCH
Input IN
Output OUT
Push PUSH
Pop POP
Data Transfer Instructions with Different Addressing Modes
Assembly
Mode Convention Register Transfer
Direct address LD ADR AC M[ADR]
Indirect address LD @ADR AC  M[M[ADR]]
Relative address LD $ADR AC  M[PC + ADR]
Immediate operand LD #NBR AC  NBR
Index addressing LD ADR(X) AC  M[ADR + XR]
Register LD R1 AC  R1
Register indirect LD (R1) AC  M[R1]
Autoincrement LD (R1)+ AC  M[R1], R1  R1 + 1
Autodecrement LD -(R1) R1  R1 - 1, AC  M[R1]
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 DATA MANIPULATION INSTRUCTIONS
Three Basic Types: Arithmetic instructions
Logical and bit manipulation instructions
Shift instructions
Arithmetic Instructions
Name Mnemonic
Increment INC
Decrement DEC
Add ADD
Subtract SUB
Multiply MUL
Divide DIV
Add with Carry ADDC
Subtract with Borrow SUBB
Negate(2’s Complement) NEG

Logical and Bit Manipulation Instructions Shift Instructions

Name Mnemonic Name Mnemonic
Clear CLR Logical shift right SHR
Complement COM Logical shift left SHL
AND AND Arithmetic shift right SHRA
OR OR Arithmetic shift left SHLA
Exclusive-OR XOR Rotate right ROR
Clear carry CLRC Rotate left ROL
Set carry SETC Rotate right thru carry RORC
Complement carry COMC Rotate left thru carry ROLC
Enable interrupt EI
Disable interrupt DI 42
 PROGRAM CONTROL INSTRUCTIONS
+1
In-Line Sequencing
(Next instruction is fetched from the
PC next adjacent location in the memory)

Address from other source; Current Instruction, Stack, etc

Branch, Conditional Branch, Subroutine, etc
Program Control Instructions
Name Mnemonic
Branch BR
Jump JMP
Skip SKP
Call CALL * CMP and TST instructions do not retain their
Return RTN results of operations(- and AND, respectively).
Compare(by - ) CMP They only set or clear certain Flags.
Test (by AND) TST

Status Flag Circuit A B

8 8
c7
8-bit ALU
c8
F7 - F0
V Z S C
F7
Check for 8
zero output
F 43
CONDITIONAL BRANCH INSTRUCTIONS
Mnemonic Branch condition Tested condition
BZ Branch if zero Z=1
BNZ Branch if not zero Z=0
BC Branch if carry C=1
BNC Branch if no carry C=0
BP Branch if plus S=0
BM Branch if minus S=1
BV Branch if overflow V=1
BNV Branch if no overflow V=0
Unsigned compare conditions (A - B)
BHI Branch if higher A>B
BHE Branch if higher or equal AB
BLO Branch if lower A<B
BLOE Branch if lower or equal AB
BE Branch if equal A=B
BNE Branch if not equal AB
Signed compare conditions (A - B)
BGT Branch if greater than A>B
BGE Branch if greater or equal AB
BLT Branch if less than A<B
BLE Branch if less or equal AB
BE Branch if equal A=B
BNE Branch if not equal AB

44
 SUBROUTINE CALL AND RETURN
SUBROUTINE CALL Call subroutine
Jump to subroutine
Branch to subroutine
Branch and save return address
Two Most Important Operations are Implied;

* Branch to the beginning of the Subroutine

- Same as the Branch or Conditional Branch

* Save the Return Address to get the address

of the location in the Calling Program upon
exit from the Subroutine
- Locations for storing Return Address: CALL
SP  SP - 1
• Fixed Location in the subroutine(Memory) M[SP]  PC
• Fixed Location in memory PC  EA
• In a processor Register
• In a memory stack RTN
- most efficient way PC  M[SP]
SP  SP + 1
45
 PROGRAM
Types of Interrupts:
INTERRUPT
External interrupts
External Interrupts initiated from the outside of CPU and Memory
- I/O Device -> Data transfer request or Data transfer complete
- Timing Device -> Timeout
- Power Failure

Internal interrupts (traps)

Internal Interrupts are caused by the currently running program
- Register, Stack Overflow
- Divide by zero
- OP-code Violation
- Protection Violation

Software Interrupts
Both External and Internal Interrupts are initiated by the computer Hardware.
Software Interrupts are initiated by texecuting an instruction.
- Supervisor Call -> Switching from a user mode to the supervisor mode
-> Allows to execute a certain class of operations
which are not allowed in the user mode

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 INTERRUPT PROCEDURE
Interrupt Procedure and Subroutine Call
- The interrupt is usually initiated by an internal or
an external signal rather than from the execution of
an instruction (except for the software interrupt)

- The address of the interrupt service program is

determined by the hardware rather than from the
address field of an instruction

- An interrupt procedure usually stores all the

information necessary to define the state of CPU
rather than storing only the PC.

The state of the CPU is determined from;

Content of the PC
Content of all processor registers
Content of status bits
Many ways of saving the CPU state depending on the CPU architectures

47