I/O organization - Accessing I/O devices,

interrupts - handling multiple devices, Direct

memory
access
 INPUT/OUTPUT ORGANIZATION

• A general purpose computer should have the ability to

exchange information with a wide range of devices in varying
environments.

• Computers are extensively used to communicate with other

computers over the Internet and access information around
the globe.

• We are going to discuss about various ways in which I/O

operations are performed.
 Accessing I/O Devices

• Most modern computers use single bus arrangement for

connecting I/O devices to CPU & Memory.

• A bus is a shared communication link, which uses one set of

wires to connect multiple subsystems

• The bus enables all the devices connected to it to exchange

information

• • Bus consists of 3 set of lines :

• Address, Data, Control
Accessing I/O Devices
 Accessing I/O Devices

• Each I/O device is assigned a unique set of address.

• Address lines are used to carry the physical address in

memory where information is stored

• The data lines of the bus carry information between the source
and the destination-bidirectional

• The control lines are used to carry control & time signals-
indicate what type of information is on the data lines.
 Accessing I/O Devices

• To communicate with a particular device, the processor

places a device address on address lines

• Device which recognizes this address responds to the

commands issued on the Control lines.

• Processor requests for either Read / Write

• The data will be placed on Data lines

 Accessing I/O Devices

Eg:
• if DATAIN is the address of the input buffer of the keyboard
Move DATAIN, R0
Reads data from DATAIN and stores it in register R0
• And DATAOUT is the address of the output buffer of the
display/printer
Move R0, DATAOUT
• Sends contents of register R0 to DATAOUT
 I/O Interface
• I/O devices connected to a computer need special communication
links to resolve the differences that exist between the CPU and each
peripheral.

• The main difference is that the data transfer rate of peripherals is

usually slower than the transfer rate of CPU and consequently, a
synchronization mechanism may be needed.

• To Resolve these differences, computer systems include special

hardware components between the CPU and Peripherals to supervises
and synchronizes all input and out transfers.

• These components are called Interface Units because they interface

between the processor bus and the peripheral devices.
I/O Interface for Input Device
 I/O Interface

• Address Decoder: Enables the device to recognize its address

when this address appears on the address lines.
• Data Registers(buffering): holds the data being transferred
to/from the processor(Data IN, Data OUT)
• Status Registers: Contains information relevant to the
operation of the I/O device.(SIN,SOUT)
• Control Unit: Coordinate I/O transfer
• The address decoder, data and status registers and controls
required to coordinate I/O transfers constitutes interface circuit
 Input Output Mechanisms

• Two commonly used mechanisms for implementing I/O

operations are:

• Interrupts and
• Direct memory access
 Interrupts

• Two commonly used mechanisms for implementing I/O

operations are:

• Interrupts and
• Direct memory access
 Interrupts
• It is mechanism used for the communication between CPU and
I/O devices.

• There are many situations where processor can perform other

tasks while waiting for an I/O device to become ready.

• To effective utilize the CPU, we can arrange the I/O device to

send a signal when it is ready –knowns as interrupt.

• Interrupt-request line is usually dedicated for this purpose.

 Interrupts

• Using interrupt we are ideally eliminating WAIT period.

• Routine executed in response to an interrupt request is

called interrupt-service routine.

• When interrupt occurs there should be a transfer of control

to Interrupt Service Routine

•.
 Interrupts

• All the registers, flags, program counter values are saved

by the processor before running ISR.

• Execution of the interrupted program resumes, once the

execution ISR(interrupt service routine) completes.

• The time required to save status & restore contribute to

execution overhead -Interrupt Latency.
 Interrupt Hardware
• Most computers are likely to have several I/O devices that can
request an interrupt.

• A single interrupt-request line may be used to serve these n

devices.

• All devices are connected to the request line through a switch.

• The device which wants to request an interrupt closes its

switch and the interrupt request signal received by the
processor goes to 1
 ENABLING AND DISABLING
INTERRUPTS
• As interrupts can occur at any time and affect the
execution of the currently running program, some times it
is necessary to disable the interrupt and enable it later on
in the program

• All computers fundamentally should be able to enable and

disable interruptions as desired.

• Consider the case of a single interrupt request signal from

one device
 ENABLING AND DISABLING
INTERRUPTS
• It is essential to ensure this active request signal
doesn’t lead to
successive interruptions, causing system to enter an infinite loop.

• Several mechanisms are available to solve this problem.

• Three methods of Controlling Interrupts (single device) are:

• Ignoring interrupt
• Disabling interrupts
• Special Interrupt request line
 ENABLING AND DISABLING
INTERRUPTS

Ignoring interrupt
• Processor hardware ignores the interrupt request line until
the execution of the first instruction of the ISR completed.

• Using an interrupt disable instruction after the first

instruction of the ISR – no further interrupts

• An interrupt enable instruction is the last instruction in

the ISR before Return -from -interrupt instruction
 ENABLING AND DISABLING
INTERRUPTS
Disabling Interrupts
• Processor automatically disables interrupts before starting the
execution of the ISR

• The processor saves the contents of PC and PS (Processor Status

register) before performing interrupt disabling

• The interrupt-enable bit in PS is set to 0 – no further interrupts

allowed.

• When return from interrupt instruction is executed the contents of

the PS are restored from the stack, and the interrupt enable is set to
1 enabling interrupts
 ENABLING AND DISABLING
INTERRUPTS
Special Interrupt line
• Special interrupt request line for which the interrupt
handling circuit responds only to the leading edge of the
signal

• Edge –triggered

• Processor receives only one request regardless of how long

the line is activated

• No separate interrupt disabling instructions

 ENABLING AND DISABLING
INTERRUPTS
Special Interrupt line
• Special interrupt request line for which the interrupt
handling circuit responds only to the leading edge of the
signal

• Edge –triggered

• Processor receives only one request regardless of how long

the line is activated

• No separate interrupt disabling instructions

 Handling multiple devices
• Multiple devices capable of initiating interrupts are connected
to the processor.

• While handling multiple devices, the issues concerned are:

• How can the processor recognize the device requesting an interrupt?

• How can the processor obtain the starting address of the appropriate
routine?
• Should a device be allowed to interrupt the processor while another
interrupt is being serviced?
• How should two or more simultaneous interrupt requests be handled?
 Handling multiple devices

• Techniques for handling multiple device

interrupts are:

• Polling
• Vectored Interrupts
• Interrupt Nesting
• Daisy Chaining
 Polling Scheme
• The IRQ (interrupt request) bit in the device’s
status register is set when a device is
requesting an interrupt.

• ISR Polls the I/O devices connected to the bus to

identify interrupting device.

• The first device encountered with the IRQ bit set

is serviced and the appropriate subroutine is
invoked.
 Vectored Interrupts
• Introduced to reduce time involved in the polling process.

• On receiving IRQ if the processor is ready to handle the

interrupting device, it activates INTA(interrupt Acknw) signal

• In response the I/O device sends its special code known as

interrupt vector code

• The code contains the: identification of the device, and starting

address for the ISR.

•The ISR is loaded by the processor to PC

 Interrupt nesting
• Disabling Interrupts during the execution of the ISR may not
favor devices which need immediate attention.

• I/O devices are organized in a priority structure.

• Pre-Emption of low priority Interrupt by another high priority

interrupt is known as Interrupt nesting.(also known as multiple-
level priority scheme).

• Ifthe priority of the device that activated IRQ is less than the
priority of the device whose ISR is currently running, then that
request is ignored
 Interrupt nesting
• Can be easily implemented using separate interrupt request
lines and interrupt acknowledge lines for each device

• Each of the interrupt-request lines is assigned a different priority

level.
• The processor is interrupted only by a high priority device
 Daisy Chaining

• The interrupt request line INTR is common to all the devices

• The interrupt acknowledgement line INTA is connected to
devices in a DAISY CHAIN way.
• Low priority device may have a danger of STARVATION
Direct Memory
Access
 Direct Memory Access
•A Mechanism incorporated to resolve the overheads occurred in I/O
transfer processes like interrupts.

•A special control unit- DMA controller allows transfer of a block of

data directly between an external device and the main memory,
without continuous intervention by the processor.

• DMA controller is a part of the I/O device interface and performs

functions that normally be carried out by the processor when
accessing main memory.

• The operations of DMA controller are under the control of a program

executed by the processor
 DMA Controller-WORKING
• To initiate transfer of a block of words, the processor sends the
following data to DMA controller
1.The starting address of the memory block
2.The word count in the block
3. mode of transfer such as read or write

• DMA controller must increment the memory address for successive

words in the block and keep track of the number of transfers.

• After transferring entire block it sends an interrupt to the processor

 Direct Memory Access
• Whilea DMA transfer is taking place, the processor can be
used to execute another program.

• After the DMA transfer is completed, the processor can return

to the program that requested the transfer.

• In DMA interface 3 registers are used:

 First register stores the starting address
 Second register stores Word count
 Third register contains status and control flags
 CONFLICTS IN DMA
• Memory accesses by the processor and DMA Controller are
interwoven.
• DMA devices have higher priority than processor over BUS control

Conflicts in DMA:
• Processor and DMA or Two DMA controllers, try to use the Bus at the same time
to access the main memory

• To resolve this, an arbitration procedure is implemented on the bus

to coordinate the activities of all devices requesting memory
transfers.
 BUS Arbitration
• The device that is allowed to initiate data transfers on the bus at
any given time is called the bus master.

• When current master relinquishes control of the bus, another

device can aquire this status

• Arbitration is the process by which the next device to become

the bus master is selected and bus master ship is transferred to
it.

• The two approaches are:

• centralized
• distributed arbitrations.
 Centralized BUS Arbitration

• The bus arbiter may be the processor or a separate controller connected to the bus.

• Processor is normally the bus master unless it grants master ship to one of DMA
Controllers .

• The arbitration scheme used by centralized bus arbitration approach is daisy chaining

• It is simple and cheaper method. All masters make use of the same line for bus request.
 Centralized BUS Arbitration

• In response to the bus request the Processor sends a bus grant if the bus is
free

• The bus grant signal serially propagates through each master until it
encounters the first one that is requesting access to the bus.

• This master blocks the propagation of the bus grant signal, gains control of
the bus. And activities the bus busy line to indicate other controllers that it
is using the bus.
 Distributed Arbitration

• Distributed Arbitration: all devices waiting to use bus participate in the

selection of the next bus master.

• In this scheme each device on the bus is assigned a4-bit identification

number.

• when one or more devices request for the control of bus, they assert the
start-arbitration signal and place their 4-bit ID numbers on arbitration
lines.

• A winner is selected as a result of interaction among the signals

transmitted over the lines by all contenders.