Design of Combinational Logic Circuits

Design Procedure, Binary Adder-Subtractor, Parallel

Adder, Binary Multiplier, MagnitudeComparator-4 bit,
Decoders, Encoders, Multiplexers, De-multiplexer, Parity
generator and checker. Application of Mux and Demux.

MODULE- 4 ECE2003 – DIGITAL LOGIC DESIGN 2

INTRODUCTION TO
COMBINATIONAL
LOGIC CIRCUITS

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 INTRODUCTION TO
COMBINATIONAL LOGIC
The digital system consists of two types of
circuits,
 Combinational circuit:
 consists of logic gates
 output at any time is determined from
the present combination of inputs.

 Sequential circuit:
 comprises both logic gates and the state
of storage elements such as flip-flops.
 The output of a sequential circuit
depends not only on present value of
inputs but also on past state of inputs.
ECE2003 – DIGITAL LOGIC DESIGN 4
 INTRODUCTION TO
COMBINATIONAL LOGIC
 A combinational circuit consists of input
variables, logic gates, and output variables.

 The logic gates accept signals from inputs

and output signals are generated according
to the logic circuits employed in it.

 Binary information from the given data

transforms to desired output data in this
process.

 Both input and output are obviously the

binary signals, i.e., either logic 1 or logic 0.
ECE2003 – DIGITAL LOGIC DESIGN 6
 INTRODUCTION TO
COMBINATIONAL LOGIC

Block diagram of a combinational logic

circuit

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 INTRODUCTION TO
COMBINATIONAL LOGIC

 For n number of input variables to a

combinational circuit, 2n possible
combinations of binary input states are
possible.

 For each possible combination, there is one

and only one possible output combination.

 A combinational logic circuit can be

described by m Boolean functions and each
output can be expressed in terms of n input
variables.
MODULE- 4 ECE2003 – DIGITAL LOGIC DESIGN 8
 DESIGN
PROCEDURE

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 DESIGN PROCEDURE
 Any combinational circuit can be designed
by the following steps of design procedure.
[Link] problem statement.
[Link] the number of input and output
variables.
[Link] input and output variables are assign with
letter symbols.
[Link] of a truth table for the given logic.
[Link] simplified Boolean expression is obtained
by any method of minimization—algebraic
method, Karnaugh mapLOGIC
ECE2003 – DIGITAL method.
DESIGN 24
 DESIGN PROCEDURE
EXAMPLE-1:
 Design a combinational circuits with three
input variables that will produce a logic-1
output when more than one input variables
are HIGH state.
Solution:
STEP1: The problem statement.
Design a combinational circuits with three input
variables that will produce a logic-1 Output when
more than one input variables are HIGH.

STEP2: Identify the input and output variables

No. of inputs required: 3
No. of output required: 1
ECE2003 – DIGITAL LOGIC DESIGN 25
 DESIGN PROCEDURE

STEP3: The input & outputs are assign with letter

symbols
Letter symbol for inputs: A, B, C
Letter symbol for output: Y

STEP4: Construction of a truth table for the given logic

ECE2003 – DIGITAL LOGIC DESIGN 26

 DESIGN PROCEDURE

STEP5: obtain the simplified expression for output

variable using K-map simplification

STEP6: A logic diagram is realized from the simplified

Boolean expression using logic gates
C
0 1
AB
00 0 0
01
0 1
11
1 1
10
0 1 Y = (AB)+(AC)+(BC)
MODULE- 4 ECE2003 – DIGITAL LOGIC DESIGN 27
 DESIGN PROCEDURE
EXERCISES
 Design a circuit with 4 inputs that has
outputs with a binary value equal to the
number of inputs that are HIGH.

 A logic circuit accepts two 3-bit numbers

and generates a logic output only when the
two 3-bit numbers applied to the circuit are
equal. Design the logic circuit.

 Design a logic circuit that will produce a 1

only when the number of 1’s in a set of four
inputs variables, A, B, and C, D are even 31
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 BINARY
ADDER

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 BINARY ADDER
HALF ADDER
 A half-adder is a combinational circuit that
can be used to add two binary bits.

 It has two inputs that represent the two bits

to be added and two outputs, with one
producing the SUM output and the other
producing the CARRY. Inputs Outputs
Carry Sum
A B
(C) (S)
0 0 0 0
0 1 0 1
BLOCK DIAGRAM 1 0 0 1
1 1 TRUTH
1 TABLE 0
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 BINARY ADDER
HALF ADDER

 The Boolean expressions for the SUM and

CARRY outputs are given by the equations,
Sum, S = A’B+ AB’= AB
Carry, C = A . B
MODULE- 4 ECE2003 – DIGITAL LOGIC DESIGN 34
 BINARY ADDER
HALF ADDER
 The first one representing the SUM output is
that of an EX-OR gate, the second one
representing the CARRY output is that of an
AND gate.

LOGIC DIAGRAM

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 BINARY ADDER
FULL ADDER
 The full adder circuit overcomes the
limitation of the half-adder, which can be
used to add two bits only.

 A full adder is a combinational circuit that

forms the arithmetic sum of three input
bits.

 It consists of 3 inputs and 2 outputs. Two of

the input variables, represent the
significant bits to be added.
MODULE- 4 ECE2003 – DIGITAL LOGIC DESIGN 36
 BINARY ADDER
FULL ADDER

Inputs Outputs
Sum Carry
A B Cin
(S) (Cout)
0 0 0 0 0
0 0 1 1 0
0 1 0 1 0
0 1 1 0 1
1 0 0 1 0
1 0 1 0 1
1 1 0 0 1
LOGIC DIAGRAM 1 1 1 1 1

TRUTH TABLE
MODULE- 4 ECE2003 – DIGITAL LOGIC DESIGN 37
 BINARY ADDER
FULL ADDER
K-MAP

 The Boolean expressions for the SUM and

CARRY outputs are given by the equations,
Sum, S= A’B’Cin+ A’BC’in + AB’C’in
+ ABCin
MODULE- 4 Carry, C = AB+ AC + BC
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 BINARY ADDER
FULL ADDER
 The logic diagram for the above functions is
shown as,

Implementation of full-adder in Sum of Products

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 BINARY ADDER
FULL ADDER
 The logic diagram of the full adder can also
be implemented with two half-adders and
one OR gate.

 The S output from the second half adder is

the exclusive-OR of Cin and the output of
the first half-adder, giving

Sum = A’BC’in + AB’C’in + ABCin +

A’B’Cin .
= C’in (A’B+AB’) + Cin (AB+A’B’)
MODULE- 4
= C’ (A’B+AB’) + C (A’B+AB’)’ 40
ECE2003 – DIGITAL LOGIC DESIGN
 BINARY ADDER
FULL ADDER

Carry, Cout = AB+ ACin+ BCin.

= AB+ ACin+ BCin (A +A’)
= ABCin+ AB+ ACin+ A’BCin
= AB (Cin+1) + ACin+ A’BCin
[Cin+1= 1]
= AB+ ACin+ A’BCin
= AB+ ACin (B+B’) + A’BCin
= ABCin+ AB+ A’BCin+ AB’Cin
= AB (Cin+1) + A’BCin+ AB’Cin
[Cin+1= 1]
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 BINARY ADDER
FULL ADDER

mplementation of full adder with two half-adders and an OR gate

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 BINARY
SUBTRACTOR

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 BINARY SUBTRACTOR
HALF SUBTRACTOR
 A half Subtractor is a combinational circuit
that can be used to subtract one binary
digit from another to produce a
DIFFERENCE output and a BORROW output.

 The BORROW output here specifies whether

a ‘1’ has been borrowed to perform the
subtraction.

Block schematic of half

Subtractor
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 BINARY SUBTRACTOR
HALF SUBTRACTOR
 The truth table of half Subtractor, showing
all possible input combinations and the
corresponding outputs are shown below.

Input Output
Difference Borrow
A B
(D) (Bout)
0 0 0 0

0 1 1 1
1 0 1 0
1 1 0 0
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 BINARY SUBTRACTOR
HALF SUBTRACTOR
 K-map simplification for half Subtractor:

 The Boolean expressions for the

DIFFERENCE and BORROW outputs are
given by the equations,
Difference, D = A’B+ AB’= A  B
Borrow, Bout = A’ . B
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 BINARY SUBTRACTOR
HALF SUBTRACTOR

Logic Implementation of Half-Subtractor

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 BINARY SUBTRACTOR
HALF SUBTRACTOR
 Comparing a half Subtractor with a half-
adder, we find that the expressions for the
SUM and DIFFERENCE outputs are just the
same.

 The expression for BORROW in the case of

the half-Subtractor is also similar to what
we have for CARRY in the case of the half-
adder.

 If the input A i.e. the minuend is

complemented, an AND gate can be used
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 BINARY SUBTRACTOR
FULL SUBTRACTOR

 A full Subtractor performs subtraction

operation on two bits, a minuend and a
subtrahend, and also takes into
consideration whether a ‘1’ has already
been borrowed by the previous adjacent
lower minuend bit or not.

 As a result, there are three bits to be

handled at the input of a full Subtractor,
namely the two bits to be subtracted and a
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 BINARY SUBTRACTOR
FULL SUBTRACTOR

 There are two outputs, namely the

DIFFERENCE output D and the BORROW
output Bo. The BORROW output bit tells
whether the minuend bit needs to borrow a
‘1’ from the next possible higher minuend
bit.

Block schematic of full Subtractor

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 BINARY SUBTRACTOR
FULL SUBTRACTOR

Inputs Outputs
Difference(D Borrow(Bout
A B Bin
) )
0 0 0 0 0
0 0 1 1 1
0 1 0 1 1
0 1 1 0 1
1 0 0 1 0
1 0 1 0 0
1 1 0 0 0
1 1 1 1 1

Truth Table
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 BINARY SUBTRACTOR
FULL SUBTRACTOR
 K-map simplification for full Subtractor:

 The Boolean expressions for the

DIFFERENCE and BORROW outputs are
given by the equations,
Difference, D = A’B’Bin+ A’BB’in +
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 BINARY SUBTRACTOR
FULL SUBTRACTOR

Implementation of full Subtractor

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 BINARY SUBTRACTOR
FULL SUBTRACTOR
 The logic diagram of the full Subtractor can
also be implemented with two half
Subtractor and one OR gate.

 The difference, D output from the second

half Subtractor is the exclusive-OR of Bin
and the output of the first half Subtractor,
giving
Difference, D = A’BB’in + AB’B’in + ABBin +
A’B’Bin .
= B’in (A’B+AB’) + Bin (AB+A’B’)
= B’ECE2003
in (A’B+AB’) + Bin (A’B+AB’)’
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 BINARY SUBTRACTOR
FULL SUBTRACTOR

Borrow, Bout = A’B+ BBin+ A’Bin.

= A’B+ BBin+ A’Bin (B +B’)
= A’BBin+ A’B+ BBin+ A’B’Bin
= A’B (Bin+1) + BBin+ A’B’Bin
[Bin+1= 1]
= A’B+ BBin+ A’B’Bin
= A’B+ BBin (A+A’) + A’B’Bin
[A+A’= 1]
= A’BBin+ A’B+ ABBin+ A’B’Bin
= A’B (Bin+1) + ABBin+ A’B’Bin
[B +1= 1]
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 BINARY SUBTRACTOR
FULL SUBTRACTOR
 Therefore, we can implement full Subtractor
using two half Subtractor and OR gate as,

entation of full Subtractor with two half Subtractor and an

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 BINARY ADDER &
SUBTRACTOR
APPLICATIONS
 Adders & Subtractors are wildly used in in
computer’s ALU (Arithmetic logic unit) to
compute addition as well as CPU (Central
Processing unit) and GPU (Graphics
Processing unit) for graphics applications to
reduce the circuit complexity.

 Adder and subtractor are basically used for

performing arithmetical functions like
addition, subtraction, multiplication and
division in electronic calculators and digital
instruments.
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 BINARY ADDER &
SUBTRACTOR
APPLICATIONS

 Microcontrollers use adders for arithmetic

additions, PC (program counter) and timers.

 It is also used in microprocessors to

calculate address, table indices, increment
and decrement operators and slimier
operations

 It is also used in networking and DSP

(Digital signal processor) oriented system
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 PARALLEL ADDER

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 PARALLEL ADDER
 A single full adder is capable of adding two
one bit numbers and an input carry. In
order to add a binary number with more
than one bit an additional full adders must
be employed.

 The n-bit parallel adder can be constructed

using “n” number of full adder circuits in
parallel.

 The block diagram of n-bit parallel adder

using number of full adder circuits
connected in cascade i.e. the carry output 58
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 PARALLEL ADDER

n-bit parallel Adder

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 PARALLEL ADDER
 The 4-bit binary adder using full adder
circuits is capable of adding two 4-bit
numbers resulting in a 4-bit sum and a
carry output as shown in figure below.

4-bit binary parallel Adder

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 PARALLEL ADDER
 Since all the bits of augend and addend are
fed into the adder circuits simultaneously
and the additions in each position are
taking place at the same time, this circuit is
known as parallel adder.
 Let the 4-bit words to be added be
represented by, A3 A2 A1 A0= 1 1 1 1 and B3
B2 B1 B0= 0 0 1 1.

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 PARALLEL ADDER

Logic diagram of 4-bit parallel

adder
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 PARALLEL ADDER

 The bits are added with full adders, starting

from the least significant position, to form
the sum bit and carry bit.

 The input carry C0 in the least significant

position must be 0. The carry output of the
lower order stage is connected to the carry
input of the next higher order stage.

 Hence this type of adder is called ripple-

carry adder.
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 PARALLEL ADDER
 In the least significant stage, A0, B0 and C0
(which is 0) are added resulting in sum S0
and carry C1. This carry C1 becomes the
carry input to the second stage.

 Similarly in the second stage, A1, B1 and C1

are added resulting in sum S1 and carry C2,
in the third stage, A2, B2 and C2 are added
resulting in sum S2 and carry C3, in the third
stage, A3, B3 and C3 are added resulting in
sum S3 and C4, which is the output carry.
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 BINARY
MULTIPLIER

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 BINARY MULTIPLIER

 Multiplication of binary numbers is

performed in the same way as in
decimal numbers.

 The multiplicand is multiplied by each bit

of the multiplier starting from the least
significant bit.

 Each such multiplication forms a partial

product. Such partial products are
shifted one position to left.
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 BINARY MULTIPLIER
2-Bit by 2-Bit Multiplier

 Consider the multiplication of two 2-bit

numbers. The multiplicand bits are B1 and
B0, the multiplier bits are A1 and A0, and the
product is P3, P2, P1 and P0.

 The first partial product is formed by

multiplying B0 by A1A0. The multiplication of
two bits such as A0 and B0 produces a 1 if
both bits are 1; otherwise, it produces a 0.

 This is identical to an AND operation.

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 BINARY MULTIPLIER
2-Bit by 2-Bit Multiplier
 The second partial product is formed by
multiplying A1 by B1B0 and shifted one
position to the left. The two partial products
are added with two half adder (HA) circuits.

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 BINARY MULTIPLIER
2-Bit by 2-Bit Multiplier

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 BINARY MULTIPLIER
2-Bit by 2-Bit Multiplier
 Usually there are more bits in the partial
products and it is necessary to use full
adders to produce the sum of the partial
products.

 The least significant bit of the product does

not have to go through an adder since it is
formed by the output of the first AND gate.
 A combinational circuit binary multiplier
with more bits can be constructed in a
similar fashion. A bit of the multiplier is
ANDed with each bit of the multiplicand in 84
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 BINARY MULTIPLIER
4-Bit by 4-Bit Multiplier

 The binary output in each level of AND

gates are added with the partial product of
the previous level to form a new partial
product. The last level produces the final
product result.

 Consider a multiplier circuit that multiplies

a binary number of four bits by a number of
four bits.

 Let the multiplicand be represented by B3,

B , B , B and the multiplier by A , A , A ,
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 BINARY MULTIPLIER
4-Bit by 4-Bit Multiplier

 Since 4x4 multiplication process we need

16 AND gates and three 4-bit parallel
adders to produce a product of eight bits.

 As shown in figure each shifted multiplicand

which is multiplied by either 0 or 1
depending on the corresponding, multiplier
bit is called partial product.

 The final 8-bit product is obtained by

adding all partial products.
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 BINARY MULTIPLIER
4-Bit by 4-Bit Multiplier

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 BINARY MULTIPLIER
4-Bit by 4-Bit Multiplier
 The multiplication of B0 and A0 produces a 1
if both bits are 1; otherwise it produces 0.
This is identical to AND gates operation.
Therefore the partial products can be
implemented with AND gates.

 The 4-bit partial products are added using

4-bit parallel adder. During addition of first
partial product three most significant bits of
it are added to the second partial product.
 As we take only three bits from the partial
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 BINARY MULTIPLIER
4-Bit by 4-Bit Multiplier
 The three most significant bits and carry
out of first partial sum are then added to
the third partial product.

 Finally the three most significant bits and

carry out of second partial sum are added
to the fourth partial product the carryout
and third sum represents the five most
significant bits of the product.

 Least significant bits of first and second

partial sum represent P1 and P2 respectively 89
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 BINARY MULTIPLIER
4-Bit by 4-Bit Multiplier

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 MAGNITUDE
COMPARATOR

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 MAGNITUDE COMPARATOR
 A magnitude comparator is a combinational
circuit that compares two given numbers (A
and B) and determines whether one is
equal to, less than or greater than the
other.
 The output is in the form of three binary
variables representing the conditions A=
B, A>B and A<B, if A and B are the two
numbers being compared.

Block diagram of magnitude comparator

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 MAGNITUDE COMPARATOR
2-Bit Magnitude Comparator
Inputs Outputs
A1 A0 B1 B0 A>B A=B A<B
0 0 0 0 0 1 0
0 0 0 1 0 0 1
0 0 1 0 0 0 1
0 0 1 1 0 0 1
0 1 0 0 1 0 0
0 1 0 1 0 1 0
0 1 1 0 0 0 1
0 1 1 1 0 0 1
1 0 0 0 1 0 0
1 0 0 1 1 0 0
1 0 1 0 0 1 0
1 0 1 1 0 0 1
1 1 0 0 1 0 0
1 1 0 1 1 0 0
1 1 1 0 1 0 0
1 1 1 1 0 1 0
Truth Table
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 MAGNITUDE COMPARATOR
2-Bit Magnitude Comparator

K-Map Simplification

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 MAGNITUDE COMPARATOR
2-Bit Magnitude Comparator

Logic Diagram
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 MAGNITUDE COMPARATOR
4-Bit Magnitude Comparator
 Let us consider the two binary numbers A
and B with four digits each. Write the
coefficient of the numbers in descending
order as,

A = A3A2A1A0
B = B 3 B2 B1 B0

 Each subscripted letter represents one of

the digits in the number. It is observed from
the bit contents of two numbers that A = B
when A = B , A = B , A = B and A = B .
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 MAGNITUDE COMPARATOR
4-Bit Magnitude Comparator

 When the numbers are binary they possess

the value of either 1 or 0, the equality
relation of each pair can be expressed
logically by the equivalence function as

Xi = Ai Bi + Ai ′ Bi ′ for i =
0, 1, 2, 3
Or, Xi = (A  B)′ Or, Xi ′ = A  B
Or, Xi = (Ai Bi ′ + Ai ′Bi )′

where, Xi =1 only if the pair of bits in

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 MAGNITUDE COMPARATOR
4-Bit Magnitude Comparator

 To satisfy the equality condition of two

numbers A and B, it is necessary that all Xi
must be equal to logic 1. This indicates the
AND operation of all Xi variables.

 In other words, we can write the Boolean

expression for two equal 4-bit numbers.
(A = B) = X3X2X1 X0. (where X = A
xnor B)

 The binary variable (A=B) is equal to 1 only

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 MAGNITUDE COMPARATOR
4-Bit Magnitude Comparator
 To determine if A is greater than or less
than B, we inspect the relative magnitudes
of pairs of significant bits starting from the
most significant bit.

 If the two digits of the most significant

position are equal, the next significant pair
of digits is compared. The comparison
process is continued until a pair of unequal
digits is found.

 It may be concluded that A>B, if the

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 MAGNITUDE COMPARATOR
4-Bit Magnitude Comparator
 In a 4-bit comparator the condition of A>B
can be possible in the following four cases:
1. If A3 = 1 and B3 = 0
2. If A3 = B3 and A2 = 1 and B2 = 0
3. If A3 = B3, A2 = B2 and A1 = 1 and B1 = 0
4. If A3 = B3, A2 = B2, A1 = B1 and A0 = 1 and
B0 = 0
 Similarly the condition for A<B can be
possible in the following four cases:
1. If A3 = 0 and B3 = 1
2. If A3 = B3 and A2 = 0 and B2 = 1
3. If A3 = B3, A2 = B2 and A1 = 0 and B1 = 1
MODULE- 4
4. If A3 = B3, A2 = B2, A1 = B1 and A0 = 0 and 134
ECE2003 – DIGITAL LOGIC DESIGN
 MAGNITUDE COMPARATOR
4-Bit Magnitude Comparator

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 MAGNITUDE COMPARATOR
4-Bit Magnitude Comparator
 Therefore, we can derive the logical
expression of such sequential comparison
by,
(A>B) = A3B3′ +X3A2B2′ +X3X2A1B1′
+X3X2X1A0B0′
(A<B) = A3′B3 +X3A2′B2 +X3X2A1′B1
+X3X2X1A0′B0

 The symbols (A>B) and (A<B) are binary

output variables that are equal to 1 when
A>B or A<B, respectively.
 The gate implementation of the three
output variables just derived is simpler than 135
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 MAGNITUDE COMPARATOR

Block diagram of 4-Bit magnitude

comparator (IC7485)
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 MAGNITUDE COMPARATOR

Logic diagram of 4-
Bit magnitude
comparator

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 MAGNITUDE COMPARATOR

Block diagram of
8-Bit magnitude
comparator

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 MAGNITUDE COMPARATOR
Applications of Magnitude Comparator
 Comparators are used in central processing
units (CPUs) and microcontrollers (ALU).
 These are used in control applications in
which the binary numbers representing
physical variables such as temperature,
position, etc. are compared with a reference
value.
 Comparators are also used as process
controllers and for Servo motor control.
 Analogue-to-Digital converters, (ADC)
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 PARITY GENERATOR
AND CHECKER

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 PARITY GENERATOR
 A Parity is a very useful tool in information
processing in digital computers to indicate
any presence of error in bit information.

 External noise and loss of signal strength

causes loss of data bit information while
transporting data from one device to other
device, located inside the computer or
externally.

 To indicate any occurrence of error, an

extra bit is included with the message
according to the total number of 1s in a set 138
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 PARITY GENERATOR

 If the extra bit is considered 0 if

the total number of 1s is even
and 1 for odd quantities of 1s in a
set of data, then it is called even
parity.

 On the other hand, if the extra bit

is 1 for even quantities of 1s and
0 for an odd number of 1s, then it
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 PARITY GENERATOR
 The message including the parity is
transmitted and then checked at the
receiving end for errors.

 An error is detected if the checked parity

does not correspond with the one
transmitted.

 The circuit that generates the parity bit in

the transmitter is called a parity generator
and the circuit that checks the parity in the
receiver is called a parity checker.
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 PARITY GENERATOR

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 PARITY GENERATOR
 A table illustrates even parity as well as odd
parity for a message consisting of three
bits. 3-bit Message
Odd Party Even Parity
A B C bit bit

0 0 0 1 0
0 0 1 0 1
0 1 0 0 1
0 1 1 1 0
1 0 0 0 1
1 0 1 1 0
1 1 0 1 0
1 1 1 0 1
Parity generator truth table for
MODULE- 4
even and odd parity
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 PARITY GENERATOR
 If the message bit combination is
designated as A, B, C and Pe, Po are the
even and odd parity respectively, then it is
obvious from table that the boolean
expressions of even parity and odd parity
are
Pe = (A  B  C) and Po = (A  B
 C)′

Pe = A’B’C+ A’BC’+ AB’C’+ ABC

= A’ (B’C+ BC’) + A (B’C’+ BC)

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 PARITY GENERATOR

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 PARITY CHECKER
 The message bits with the parity bit are
transmitted to their destination, where they
are applied to a parity checker circuit. The
circuit that checks the parity at the receiver
side is called the parity checker.

 The parity checker circuit produces a check

bit and is very similar to the parity
generator circuit. If the check bit is 1, then
it is assumed that the received data is
incorrect.

 The check bit will be 0 if the received data 144

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 PARITY CHECKER
4-Bit Received
Parity Error
A B C P Check (PEC)

0 0 0 0 0
0 0 0 1 1
0 0 1 0 1
0 0 1 1 0
0 1 0 0 1
0 1 0 1 0
0 1 1 0 0
0 1 1 1 1
1 0 0 0 1
1 0 0 1 0
1 0 1 0 0
1 0 1 1 1
1 1 0 0 0
1 1 0 1 1
1 1 1 0 1
1 1 1 1 0
Parity checker truth table for
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 PARITY CHECKER

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 PARITY CHECKER

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 PARITY CHECKER
APPLICATIONS

 Parity bit generator is used in digital

communications where the messages are
transmitted in the form of 1’s and 0’s.

 The SCSI and PCI buses use parity to detect

transmission errors, and many
microprocessor instruction caches include
parity protection.

 In serial communication contexts, parity is

usually generated and checked by interface
hardware (e.g., a UART)
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ECE2003 – DIGITAL LOGIC DESIGN
 MULTIPLEXERS

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 MULTIPLEXERS
 A Multiplexer or MUX, is a combinational
circuit with more than one input line, one
output line and more than one selection
line.

 A multiplexer selects binary information

present from one of many input lines,
depending upon the logic status of the
selection inputs, and routes it to the output
line.

 Normally, there are 2n input lines and n

selection lines whose bit combinations 149
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 MULTIPLEXERS
 A multiplexer is also called a data
selector, since it selects one of many
inputs and steers the binary information to
the output line.

Block diagram of Multiplexer

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 MULTIPLEXERS
2:1 MUX
 The 2:1 multiplexer acts like an electronic
switch that selects one of the two sources.

 The circuit has two data input lines, one

output line and one selection line, S.

 When S= 0, the upper AND gate is enabled

and I0 has a path to the output.

 When S=1, the lower AND gate is enabled

and I1 has a path to the output.
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 MULTIPLEXERS
2:1 MUX

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 MULTIPLEXERS
4:1 MUX
 A 4-to-1-line multiplexer has four (2n) input
lines, two (n) select lines and one output
line.

 It is the multiplexer consisting of four input

channels and information of one of the
channels can be selected and transmitted
to an output line according to the select
inputs combinations.

 Selection of one of the four input channel is

possible by two selection inputs.
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 MULTIPLEXERS
4:1 MUX
 Each of the four inputs I0 through I3, is
applied to one input of AND gate. Selection
lines S1 and S0 are decoded to select a
particular AND gate.

 The outputs of the AND gate are applied to

a single OR gate that provides the 1-line
output.

Truth table
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 MULTIPLEXERS
4:1 MUX
The data output is equal to I0 only if S1= 0 and
S0= 0; Y= I0S1’S0’.

The data output is equal to I1 only if S1= 0 and

S0= 1; Y= I1S1’S0.

The data output is equal to I2 only if S1= 1 and

S0= 0; Y= I2S1S0’.

The data output is equal to I3 only if S1= 1 and

S0= 1; Y= I3S1S0.
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 MULTIPLEXERS
4:1 MUX

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 MULTIPLEXERS
4:1 MUX
 To demonstrate the circuit operation,
consider the case when S1S0= 10.

 The AND gate associated with input I2 has

two of its inputs equal to 1 and the third
input connected to I2.

 The other three AND gates have at least

one input equal to 0, which makes their
outputs equal to 0.

 The OR output is now equal to the value of 156

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 MULTIPLEXERS
8:1 MUX

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 MULTIPLEXERS
MUX APPLICATIONS
 Communication system –The efficiency of
communication system can be increased
considerably using multiplexer. Multiplexer allow
the process of transmitting different type of data
such as audio, video at the same time using a
single transmission line.

 Telephone network – In telephone network,

multiple audio signals are integrated on a single
line for transmission with the help of multiplexers.
In this way, multiple audio signals can be isolated
and eventually, the desire audio signals reach the
intended recipients.

 Transmission from
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DIGITAL LOGIC DESIGN system of a 159
 MULTIPLEXERS
MULTIPLEXERS TREE
 It is possible to expand the range of input
for multiplexer beyond the available range
in the integrated circuits.

 This can be accomplished by

interconnecting several multiplexers. For
example two 8:1 mux can be used together
to form a 16:1 mux and two 16:1 mux can
be used to realize the 32:1 mux.

 Even we can realize 32:1 mux can be

realized with a smaller sized mux like 8:1 or 160
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 MULTIPLEXERS
MULTIPLEXERS TREE

8:1 Mux using 4:1 & 2:1 MUX

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 MULTIPLEXERS
MULTIPLEXERS TREE

 Here, the number of selection lines require to

implement 8:1 mux is 3 (S2,S1,S0). The select
inputs S1 and S0 of both multiplexers provided
to the selections lines of 4:1 mux i.e S1, S0.
Whereas the S3 selection input of the second
level 2:1 multiplexer is connected to S3
selection line.

 So for S2 = 0, the upper multiplexer is selected

and input lines d0 to d3 are selected according
to the selected inputs and data is transmitted
to an output through the OR gate. When S2 =
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 MULTIPLEXERS
MULTIPLEXERS TREE

16:1 Mux using 4:1 MUX

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 MULTIPLEXERS
Implementation of boolean function using MUX

Example1: Implement the following

boolean function using 8:1 mux, F (A, B, C) =
∑m (1, 3, 5, 6).
Solution:
Variables, n= 3 (A, B, C)
Select lines= 3 (S2, S1, S0)
Input lines = 23 = 8 (D0, D1, D2, D3, D4, D5,
D6, D7)

 The three variables A, B, C are applied to the

selection lines.
 The minterms to be included (1, 3, 5 and 7) are
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 MULTIPLEXERS
Implementation of boolean function using MUX

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 MULTIPLEXERS
Implementation of boolean function using MUX

Example2: Implement the following

boolean function using 4:1 multiplexer, F
(A, B, C) = ∑m (1, 3, 5, 6).
Solution:
Variables, n= 3 (A, B, C)
Select lines= n-1 = 2 (S1, S0)
2n-1 to MUX i.e., 22 to 1 = 4 to 1 MUX
Input lines= 2n-1 = 22 = 4 (D0, D1, D2, D3)
Implementation table:
Apply variables B and C to the select lines. The
procedures for implementing the function are:
 List the input of the multiplexer
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 MULTIPLEXERS
Implementation of boolean function using MUX
The first half of the minterms is associated
with A’ and the second half with A. The given
function is implemented by encircling the
minterms of the function and applying the
following rules to find the values for the inputs
of the multiplexer.
1. If both the minterms in the column are not circled,
apply 0 to the corresponding input.
2. If both the minterms in the column are circled,
apply 1 to the corresponding input.
3. If the bottom minterm is circled and the top is not
circled, apply A to the input.
4. If the top minterm is circled and the bottom is not
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 MULTIPLEXERS
Implementation of boolean function using MUX

Implementation table

Truth table

Mux implementation
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 MULTIPLEXERS
Implementation of boolean function using MUX

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 MULTIPLEXERS
Implementation of boolean function using MUX

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 DEMULTIPLEXERS

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 DEMULTIPLEXERS
 Demultiplexer means one into many.
Demultiplexing is the process of taking
information from one input and transmitting
the same over one of several outputs.

 A demultiplexer is a combinational logic

circuit that receives information on a single
input and transmits the same information
over one of several (2n) output lines.

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 DEMULTIPLEXERS

 The block diagram of a demultiplexer has

one input signal, ‘n’ select signals and 2n
output signals.

 The select inputs determine to which output

the data input will be connected.

 As the serial data is changed to parallel

data, i.e., the input caused to appear on
one of the n output lines, the demultiplexer
is also called a “data distributer” or a
“serial-to-parallel converter”.
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 DEMULTIPLEXERS
1:4 DEMUX
 A 1-to-4 demultiplexer has a single input,
Din, four outputs (Y0 to Y3) and two select
inputs (S1 and S0).

 The input variable Din has a path to all four

outputs, but the input information is
directed to only one of the output lines.

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 DEMULTIPLEXERS
1:4 DEMUX

Din S1 S0 Y0 Y1 Y2 Y3
0 0 0 0 0 0 0
1 0 0 1 0 0 0
0 0 1 0 0 0 0
1 0 1 0 1 0 0
0 1 0 0 0 0 0
1 1 0 0 0 1 0
0 1 1 0 0 0 0
1 1 1 0 0 0 1

Truth table of 1-to-4 line Demultiplexer

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 DEMULTIPLEXERS
1:4 DEMUX

 From the truth table, it is clear that the data

input, Din is connected to the output Y0,
when S1= 0 and S0=0 and the data input is
connected to output Y1 when S1=0 and
S0=1.
 Similarly, the data input is connected to
output Y2 and Y3 when S1=1 and S0=0 and
when S1=1 and S0=1, respectively.
 Also, from the truth table, the expression
for outputs can be written as follows,
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 DEMULTIPLEXERS
1:4 DEMUX

Logic diagram of 1-to-4 line demultiplexer

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 DEMULTIPLEXERS
1:4 DEMUX

 Now, using the above expressions, a 1-to-4

line demultiplexer can be implemented
using four 3-input AND gates and two NOT
gates.

 Here, the input data line Din, is connected to

all the AND gates.

 The two select lines S1, S0 enable only one

gate at a time and the data that appears on
the input line passes through the selected
gate to the associated output line.
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 DEMULTIPLEXERS
1:8 DEMUX
 A 1-to-8 line demultiplexer has a single
input, Din, eight outputs (Y0 to Y7) and three
select inputs (S2, S1 and S0). It distributes
one input line to eight output lines based
on the
D select
in S 2 S inputs.
1 S Y0 Y Y Y7 Y Y6 Y Y 5 4 3 2 1 0

0 x x x 0 0 0 0 0 0 0 0
1 0 0 0 0 0 0 0 0 0 0 1
1 0 0 1 0 0 0 0 0 0 1 0
1 0 1 0 0 0 0 0 0 1 0 0
1 0 1 1 0 0 0 0 1 0 0 0
1 1 0 0 0 0 0 1 0 0 0 0
1 1 0 1 0 0 1 0 0 0 0 0
1 1 1 0 0 1 0 0 0 0 0 0
1 1 1 1 1 0 0 0 0 0 0 0
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 DEMULTIPLEXERS
1:8 DEMUX
 From the above truth table, it is clear that
the data input is connected with one of the
eight outputs based on the select inputs.

 Now from this truth table, the expression

for eight outputs can be written as follows:

Y0= S2’S1’S0’Din Y4= S2 S1’S0’Din

Y1= S2’S1’S0Din Y5= S2 S1’S0Din
Y2= S2’S1S0’Din Y6= S2 S1S0’Din
Y3= S2’S1S0Din Y7= S2S1S0Din
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 DEMULTIPLEXERS
1:8 DEMUX
 Now using the above expressions, the logic
diagram of a 1-to-8 demultiplexer can be
drawn as shown.

 Here, the single data line, Din is connected

to all the eight AND gates, but only one of
the eight AND gates will be enabled by the
select input lines.

 For example, if S2S1S0= 000, then only AND

gate-0 will be enabled and thereby the data
input, Din will appear at Y0. Similarly, the 181
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 DEMULTIPLEXERS
1:8 DEMUX

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 DEMULTIPLEXERS
DEMULTIPLEXERS TREE
 Example: Design 1:8 demultiplexer using 1:4 & 1:2
DEMUX.

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 DEMULTIPLEXERS
IMPLEMENTATION OF BOOLEAN EXPRESSION USING DEMUX
Example1: Implement the following boolean function
using 1:8 Demux. F (A, B, C) = ∑m (1, 3, 5, 6).

Inputs Output
s
A B C Y
0 0 0 0
0 0 1 1
0 1 0 0
0 1 1 1
1 0 0 0
1 0 1 1
1 1 0 1
1 1 1 0
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 DEMULTIPLEXERS
IMPLEMENTATION OF BOOLEAN EXPRESSION USING DEMUX

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 DEMULTIPLEXERS
IMPLEMENTATION OF BOOLEAN EXPRESSION USING DEMUX
Example2: Implement full subtractor using demux

Inputs Outputs
Difference( Borrow(Bou
A B Bin
D) t)

0 0 0 0 0
0 0 1 1 1
0 1 0 1 1
0 1 1 0 1
1 0 0 1 0
1 0 1 0 0
1 1 0 0 0
1 1 1 1 1

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 DEMULTIPLEXERS
IMPLEMENTATION OF BOOLEAN EXPRESSION USING DEMUX

Full Subtractor using 1:8

demux

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 DECODERS

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 DECODERS
 A decoder is a combinational circuit that
converts binary information from ‘n’ input
lines to a maximum of ‘2n’ unique output
lines.

 The encoded information is presented as ‘n’

inputs producing ‘2n’ possible outputs. The
2n output values are from 0 through 2n-1.

 A decoder is provided with enable inputs to

activate decoded output based on data
inputs. When any one enable input is
unasserted, all outputs of decoder are 189
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 DECODERS

Block diagram of decoders

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 DECODERS
2 : 4 Decoders

 A binary decoder is used when it is

necessary to activate exactly one of 2n
outputs based on an n-bit input value.

 Here the 2 inputs are decoded into 4

outputs, each output representing one of
the minterms of the two input variables.

 As shown in the truth table, if enable input

is 1 (EN= 1) only one of the outputs (Y0 –
Y3), is active for a given input.
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 DECODERS
2 : 4 Decoders

Inputs Outputs
Enable A B Y3 Y2 Y1 Y0
0 x x 0 0 0 0
1 0 0 0 0 0 1
1 0 1 0 0 1 0
1 1 0 0 1 0 0
1 1 1 1 0 0 0

Truth table

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 DECODERS
2 : 4 Decoders

Logic Diagram
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 DECODERS
3 : 8 Decoders
 A 3-to-8 line decoder has three inputs (A, B,
C) and eight outputs (Y0- Y7). Based on the 3
inputs one of the eight outputs is selected.

 This decoder is used for binary-to-octal

conversion. The input variables may
represent a binary number and the outputs
will represent the eight digits in the octal
number system.

 The output line whose value is equal to 1

represents the minterm equivalent of the
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 DECODERS
3 : 8 Decoders

Inputs Outputs
A B C Y0 Y1 Y2 Y3 Y4 Y5 Y6 Y7
0 0 0 1 0 0 0 0 0 0 0
0 0 1 0 1 0 0 0 0 0 0
0 1 0 0 0 1 0 0 0 0 0
0 1 1 0 0 0 1 0 0 0 0
1 0 0 0 0 0 0 1 0 0 0
1 0 1 0 0 0 0 0 1 0 0
1 1 0 0 0 0 0 0 0 1 0
1 1 1 0 0 0 0 0 0 0 1

Truth table

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 DECODERS
3 : 8 Decoders

Logic Diagram
MODULE-4 ECE2003 – DIGITAL LOGIC DESIGN 196
 DECODERS
Applications
 Instruction decoder is the part of the CPU

 Memory address decoding

 Decoder outputs can be used to drive a 7

segment display (TTL 74LS47)

 Binary Decoders such as binary or

BCD ,decimal or octal etc and commonly
available decoder IC’s (TTL 74LS138 3-to-8
line binary decoder or the 74ALS154 4-to-
16 line decoder)
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 DECODERS
Cascading Decoders
 Example: Design a 4 to 16 line
decoders using 2 to 4 line decoders
 To implement 4:16 decoder we need five 2:4 line
decoders.

 Decoder-1 is used to enable one of the decoder 2, 3, 4

and 5. Inputs of the first decoders are A and B i.e. MSB
inputs of 4:16 decoders.

 The inputs of decoders are connected together forming

C and D inputs of 4:16 decoders.

 When AB=00 decoder-1 is enabled, for AB=01 decoder-

2 is enabled, for AB=10 decoder-3 is selected, and for
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 DECODERS
Cascading Decoders

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 DECODERS
Realization of Boolean Expression using Decoders
 The combination of decoder and external
logic gates can be used to implement single
or multiple output function. The decoder
can have one of the two output states
either active or active high.
 For active high output :
 SOP function implementation
 When the decoder output is active high it
generates minterms for input variables (i.e) it
makes the selected output logic1. In such cases
to implement the sop function we have to take
sum of selected product terms generated by
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 DECODERS
Realization of Boolean Expression using Decoders

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 DECODERS
Realization of Boolean Expression using Decoders
 POS function implementation: When the
decoder output is active high POS function in
similar manner as per SOP function except function
output is complemented. This can be achieved by
connecting NOR gates instead of OR gates .

Single output function implementation using decoder and

gate
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 ENCODERS

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 ENCODERS
 An encoder is a combinational circuit that
converts binary information from 2n input
lines to a maximum of ‘n’ unique output
lines.
 An encoder is a digital circuit that performs
the inverse operation of a decoder. Hence,
the opposite of the decoding process is
called encoding. The general structure of
encoder circuit is,

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 ENCODERS

 Generally, digital encoders produce outputs

of 2-bit, 3-bit or 4-bit codes depending upon
the number of data input lines.

 An "n-bit" binary encoder has 2n input lines

and n-bit output lines with common types
that include 4-to-2, 8-to-3 and 16-to-4 line
configurations.

 The output lines of a digital encoder

generate the binary equivalent of the input
line whose value is equal to “1”.
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 ENCODERS
4 to 2 Encoder

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 ENCODERS
Priority Encoder

 One of the main disadvantages of standard

digital encoders is that they can generate
the wrong output code when there is more
than one input present at logic level "1".

 For example, if we make inputs D1 and D2

HIGH at logic "1" both at the same time, the
resulting output is neither at "01" or at "10"
but it will be at "11" which is an output
binary number that is different to the actual
input present.
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 ENCODERS
Priority Encoder

 One simple way to overcome this problem

is to "Priorities" the level of each input pin
and if there was more than one input at
logic level "1" the actual output code would
only correspond to the input with the
highest designated priority.

 Then this type of digital encoder is known

commonly as a Priority Encoder or P-
encoder for short.
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 ENCODERS
Priority Encoder
 A priority encoder is an encoder circuit that
includes the priority function.

 In priority encoder, if two or more inputs are

equal to 1 at the same time, the input having
the highest priority will take precedence. The
higher the subscript number, higher the
priority of the input.

 Input D3, has the highest priority. So,

regardless of the values of the other inputs,
when D3 is 1, the output for xy is 11. D2 has the
next priority level. The output is 10, if D2= 1
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 ENCODERS
4 to 2 Priority Encoder

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 ENCODERS
4 to 2 Priority Encoder

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 ENCODERS
4 to 2 Priority Encoder

4-Input Priority Encoder

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 ENCODERS
8 to 3 Priority Encoder

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 ENCODERS
Encoder Applications
(i). Keyboard Encoder
 Priority encoders can be used to reduce the
number of wires needed in a particular circuits
or application that have multiple inputs.

 For example, assume that a microcomputer

needs to read the 104 keys of a standard
QWERTY keyboard where only one key would
be pressed either “HIGH” or “LOW” at any one
time.

 One way would be to connect all 104 wires

from the individual keys on the keyboard
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 ENCODERS
Encoder Applications

 Another alternative and better way would be

to interface the keyboard to the PC using a
priority encoder.

 The 104 individual buttons or keys could be

encoded into a standard ASCII code of only 7-
bits (0 to 127 decimal) to represent each key
or character of the keyboard and then input as
a much smaller 7-bit B.C.D code directly to the
computer.

 Keypad encoders such as the 74C923 20-key

encoder are available to do just that.
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(ii) Positional Encoders
 Another more common application is in
magnetic positional control as used on ships
navigation or for robotic arm positioning etc.
 Here for example, the angular or rotary
position of a compass is converted into a
digital code by a 74LS148 8-to-3 line priority
encoder and input to the systems computer to
provide navigational data and an example of a
simple 8 position to 3-bit output compass
encoder is shown below.

 Magnets and reed switches could be used at 216

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(iii). Interrupt Requests

 Priority Encoders used for detecting interrupts

in microprocessor applications.

 Here the microprocessor uses interrupts to

allow peripheral devices such as the disk drive,
scanner, mouse, or printer etc, to
communicate with it.

 But the microprocessor can only “talk” to one

peripheral device at a time so needs some way
of knowing when a particular peripheral device
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 The processor does this by using “Interrupt
Requests” or “IRQ” signals to assign priority to
all the peripheral devices to ensure that the
most important peripheral device is serviced
first.

 The order of importance of the devices will

depend upon their connection to the priority
encoder.

 Because implementing such a system using

priority encoders such as the standard
74LS148 priority encoder IC involves additional
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