FLOORPLAN STAGE
AGENDA
Floorplan Definition &
Key Aspects
Inputs required for
Floorplanning
Steps in Floorplanning
Challenges in
Floorplanning
Commands
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DEFINITION OF FLOORPLAN
• Floorplan is the process of creating die and core boundaries
with a particular shape according to the customer
specifications,there after determining the physical placement
of the various functional blocks like macros with macro
guidelines and placing of the IO pins in the core based on the
logical netlist in the design.
• It is the first major step in the physical design flow and serves
as the bridge between the logical (netlist) and physical
(layout) representations of an integrated circuit.
• A well-optimized floorplan is essential for achieving high
performance, minimizing chip area, reducing interconnect
congestion, and ensuring efficient power distribution. Poor
floorplanning can lead to issues such as routing congestion,
KEY ASPECTS
Placement of I/O Pads and Macros: Proper alignment ensures
efficient signal flow and minimizes parasitic effects.
1.Design of Power and Ground Networks: Robust power
distribution is crucial for reliable chip operation.
2.Preparation for Routing: Ensuring adequate space for
routing minimizes congestion and improves timing.
The primary objective is to create a layout that satisfies the
design's performance goals while adhering to area and power
constraints.
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INPUTS REQUIRED FOR FLOORPLANNING
Before initiating floorplanning, several critical files and
constraints must be prepared. These inputs guide the
placement and organization of components in the chip.
1.Netlist (.v):
• A netlist is a textual description of the chip's logical
connectivity, including gates, flip-flops, and macros.
• It defines the functional relationship between components.
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CONTD
2.Technology File (techlef):
• Contains details about the technology node, such as
routing layers, design rules, and processspecific
parameters.
3.Timing Library Files (.lib):
• Defines the timing characteristics of standard cells,
including propagation delays, setup/hold times, and
power consumption.
4.Physical Library (.lef):
• Provides physical dimensions of cells and macros,
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including height, width, and pin locations.
CONTD
5.Synopsys Design Constraints (SDC):
• Specifies design constraints such as clock definitions,
input/output timing, and multi-cycle paths.
6.Tlu+ Files:
• Contains data for parasitic extraction, enabling
accurate delay and signal integrity analysis.
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STEPS IN FLOORPLANNING
Once the physical design database is created using the
imported netlist and associated library
files, the following steps are undertaken:
1. Die Size Estimation
➢Core Width and Height:
• The core dimensions are calculated based on the total
logic area and the required routing space.
➢Aspect Ratio:
• The aspect ratio determines the shape of the die and
influences routing efficiency.
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CONTD
2. I/O Pad Placement
➢Pad Sites Creation:
• Sites are allocated around the die boundary for placing I/O
pads.
➢Types of Pads:
• Power Pads: Deliver power to the chip.
• Ground Pads: Ensure stable grounding.
• Signal Pads: Facilitate data communication between the
chip and external circuits.
Proper placement minimizes electro-migration and current- 9
CONTD
3. Macro Placement
➢Manual Macro Placement:
• Suitable for designs with a few macros, where placement
is guided by connectivity and timing requirements.
➢Automatic Macro Placement:
• Used for complex designs with numerous macros,
leveraging automation tools for efficient arrangement.
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CONTD
4. Standard Cell Row Creation
• Rows are created for the placement of standard cells,
ensuring alignment and consistency across the layout.
5. Power Planning (Pre-Routing)
• The initial power and ground grid is designed to ensure
uniform power distribution and minimize IR drops.
6. Adding Physical-Only Cells
• Auxiliary cells such as filler cells, decap cells, and tap
cells are added to enhance chip performance and mitigate
signal noise.
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CONTD
7. Core and I/O Factors
• Aspect Ratio: Balances horizontal and vertical routing
resources.
• Core Utilization: Maintains sufficient space for routing
and timing closure.
• Cell Orientation: Ensures proper alignment for
manufacturing.
• Core-to-I/O Clearance: Adequate spacing avoids routing
congestion near the die boundary.
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CHALLENGES IN FLOORPLANNING
1.Area Optimization:
Balancing standard cell placement and routing space is
critical for achieving design goals.
2.Power Integrity:
Ensuring a robust power grid minimizes voltage drops and
maintains circuit reliability.
3.Signal Integrity:
Preventing crosstalk and managing switching noise is
essential for timing closure.
4.Routing Congestion:
A poorly planned floorplan can lead to severe routing issues,
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increasing delays and design iterations.
COMMANDS
1. initialize_floorplan -control_type die -core_utilization 0.65
–shape R -orientation N -side_ratio {1 1} -core_offset
{2.2 1.4}
• Creates a R shaped floor plan with core and die with
utilization 65% of the core offset {2.2 1.4}.
2. Create_pin_guide –boundary {{-0.1 100} {2.1 250}} –
name inputs [get_ports –filter “direction == in”] –
pin_spacing
3. place_pins -ports [get_ports -filter "direction == in"]
4. Create_pin_guide –boundary {{1378 100} {1379 300}} –
name outputs [get_ports –filter “direction == out”] –
pin_spacing 1 14
KEEPOUTMARGIN :
create_keepout_margin
fifo_top0/fifo_core_1/rp_fifo_mem_wrapper0/genblk1.U0_FIFO_MEM -type hard -
outer {0.28 0.9 0.9 0.9}
•This command is used to define a keep out margin OR Halo around a specified
macro or standard cell to prevent standard cell placement or routing congestion
near fifo_top0/fifo_core_1/rp_fifo_mem_wrapper0/genblk1.U0_FIFO_MEM →
Specifies the hierarchical path of the macro (e.g., FIFO memory block).
•type hard → Creates a hard keepout, meaning standard cells cannot be placed
within this region.
•outer {0.28 0.9 0.9 0.9} → Defines the outer keepout margins around the
macro in all four directions:
•Left: 0.28
•Top: 0.9
•Right: 0.9
•Bottom: 0.9
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PLACEMENT BLOCKAGE:
create_placement
BOUNDARY CELLS:blockage -type soft -boundary {{167
•create_boundary_cells
403.2} {192 724.5}}-left_boundary_cell ---
30p140hvt/BOUNDARY_LEFTBWP30P140 -
right_boundary_cell
---30p140hvt/BOUNDARY_RIGHTBWP30P140 -prefix
ENDCAP
•create_boundary_cells – Creates boundary cells to
prevent well proximity effects.
•-left_boundary_cell
---30p140hvt/BOUNDARY_LEFTBWP30P140 – Specifies the
left boundary cell.
•-right_boundary_cell
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---30p140hvt/BOUNDARY_RIGHTBWP30P140 – Specifies
TAPCELLS :
• create_tap_cells -lib_cell --30p140hvt/TAPCELLBWP30P140
-distance 30 -pattern stagger -prefix TAP -skip_fixed_cell
SANITY CHECKS :
check_io_placement :
Checks IO placement for violations and returns a
collection of affected cells.
check_pin_placement :
Performs pin placement verification.
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check_macro_pin_access :
Checks pin accessibility on a macro against itself and
horizontal/vertical cell abutment.
check_mib_alignment :
Verifies alignment of multiply instantiated block (MIB)
instances with power/ground straps, standard cell
rows, and wire tracks.
check_mib_for_pin_placement :
Detects potential pin placement issues in MIB
instances.
check_boundary_cells :
Verifies the placement of boundary cells to ensure they 18
CONCLUSION
• Floorplanning is more than just placing components on
a die; it is the foundational step that shapes the
success of an ASIC design.
• A carefully executed floorplan ensures high
performance, efficient area usage, and reliable power
distribution.By understanding the inputs, processes,
and challenges, designers can create optimized
layouts that meet design specifications and
manufacturing constraints.
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THANK YOU
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