Integrated Circuits

Unit 5
• Integrated Circuit Timer
• Timer IC 555 pin and functional block diagram
• Monostable and Astable multivibrator using the 555 IC
• Voltage Controlled Oscillator
• VCO IC 566 pin and functional block diagram and applications
• Phase Locked Loop (PLL)
• Basic Principle of PLL, Block diagram, working
• Ex-OR gates and multiplier as phase detector
• Application of PLL

Dr. Tanmay Dubey, MIET Meerut 1

Introduction to 555 Timer
• The 555 timer is a highly stable device suitable for generating
accurate time delay or oscillations.
• A single 555 timer can provide time delay ranging from microseconds
to hours whereas counter timer can have a maximum timing range of
days.
• The 555 timer can be used with supply voltage in the range of +5V to
+18V and can drive load up to 200mA.
• It is compatible with both TTL and CMOS logic circuits.
• Because of the wide range of supply voltage, the 555 timer is versatile
and easy to use in various applications.

Dr. Tanmay Dubey, MIET Meerut 2

Pin Diagram of 555 Timer

Dr. Tanmay Dubey, MIET Meerut 3

Application of 555 Timer
• Oscillator
• Phase generator
• Ramp and square wave regenerator
• Mono-shot multivibrator
• Burglar alarm, traffic light control
• Voltage monitor

Dr. Tanmay Dubey, MIET Meerut 4

Function Diagram of IC 555
• Figure shows a block diagram representation of
the 555 timer circuit.
• The circuit consists of two comparators, an SR
flip-flop, and a transistor Q1 that operates as a
switch.
• One power supply (VCC) is required for
operation, with the supply voltage typically 5 V.
• A resistive voltage divider, consisting of the
three equal-valued resistors labeled R1, is
connected across VCC and establishes the
reference (threshold) voltages for the two
comparators.
• These are VTH = 2/3VCC for comparator 1 and
VTL = 1/3VCC for comparator 2Dr. Tanmay Dubey, MIET Meerut 5
Function Diagram of IC 555
• SR flip-flop is a bistable circuit having
complementary outputs, denoted Q and Q’.
• In the set state, the output at Q is “high”
(approximately equal to VCC) and that at Q’ is
“low” (approximately equal to 0 V).
• In the other stable state, termed the reset state,
the output at Q is low and that at Q’ is high.
• The flip-flop is set by applying a high level (VCC) to
its set input terminal, labeled S.
• To reset the flip-flop, a high level is applied to the
reset input terminal, labeled R.
• Note that the reset and set input terminals of the
flip-flop in the 555 circuit are connected to the
outputs of comparator 1 and comparator 2,
respectively. Dr. Tanmay Dubey, MIET Meerut 6
Function Diagram of IC 555
• The positive-input terminal of comparator
1 is brought out to an external terminal of
the 555 package, labeled Threshold.
• Similarly, the negative-input terminal of
comparator 2 is connected to an external
terminal labeled Trigger, and the collector
of transistor Q1 is connected to a terminal
labeled Discharge.
• Finally, the Q output of the flip-flop is
connected to the output terminal of the
timer package, labeled Out

Dr. Tanmay Dubey, MIET Meerut 7

Implementing a Monostable Multivibrator
Using
the 555 IC
• Figure shows a monostable multivibrator
implemented using the 555 IC together with an
external resistor R and an external capacitor C.
• In the stable state the flip-flop will be in the reset
state, and thus its Q’ output will be high, turning
on transistor Q1.
• Transistor Q1 will be saturated, and thus vC will
be close to 0 V, resulting in a low level at the
output of comparator 1.
• The voltage at the trigger input terminal, labeled
vtrigger, is kept high (greater than VTL), and thus the
output of comparator 2 also will be low.
• Finally, note that since the flip-flop is in the reset
state, Q will be low and thus vO will be close to 0
Dr. Tanmay Dubey, MIET Meerut 8
V.
Implementing a Monostable Multivibrator
Using
the 555 IC
• To trigger the monostable multivibrator, a
negative input pulse is applied to the
trigger input terminal.
• As vtrigger goes below VTL, the output of
comparator 2 goes to the high level, thus
setting the flip-flop.
• Output Q of the flip-flop goes high, and
thus vO goes high, and output Q’ goes low,
turning off transistor Q1.
• Capacitor C now begins to charge up
through resistor R, and its voltage vC rises
exponentially toward VCC.
Dr. Tanmay Dubey, MIET Meerut 9
Implementing a Monostable Multivibrator
Using
the 555 IC
• The monostable multivibrator is now in its quasi-
stable state.
• This state prevails until vC reaches and begins to
exceed the threshold of comparator 1, VTH, at which
time the output of comparator 1 goes high,
resetting the flip-flop.
• Output Q’ of the flip-flop now goes high and turns
on transistor Q1.
• In turn, transistor Q1 rapidly discharges capacitor C,
causing vC to go to 0 V.
• Also, when the flip-flop is reset, its Q output goes
low, and thus vO goes back to 0 V.
• The monostable multivibrator is now back in its
stable state and is ready to receive a new triggering
pulse. Dr. Tanmay Dubey, MIET Meerut 10
Implementing a Monostable Multivibrator
Using
the 555 IC
• The monostable multivibrator produces an output pulse vO as
indicated in Fig.
• The width of the pulse, T, is the time interval that the
monostable multivibrator spends in the quasi-stable state; it can
be determined by reference to the waveforms in Fig. as follows:
• Denoting the instant at which the trigger pulse is applied as t =
0, the exponential waveform of vC can be expressed as

• Thus the pulse width is determined by the external components

C and R, which can be selected to have values as precise as
desired.
Dr. Tanmay Dubey, MIET Meerut 11
Astable Multivibrator Using the
555 IC
• Figure (a) shows the circuit of an astable multivibrator
employing a 555 IC, two external resistors, R A and RB, and an
external capacitor C.
• To see how the circuit operates, refer to the waveforms
depicted in Fig. (b).
• Assume that initially C is discharged and the flip-flop is set.
Thus vO is high and Q1 is off.
• Capacitor C will charge up through the series combination of R A
and RB, and the voltage across it, vC, will rise exponentially
toward VCC.
• As vC crosses the level equal to VTL, the output of comparator 2
goes low.
• This, however, has no effect on the circuit operation, and the
flip-flop remains set.
• Indeed, this state continues until vC reaches and begins to
exceed the threshold of comparator 1,Dr.VTanmay
TH . Dubey, MIET Meerut 12
Astable Multivibrator Using the
555 IC
• At this instant of time, the output of comparator 1
goes high and resets the flip-flop.
• Thus vO goes low, Q’ goes high, and transistor Q1 is
turned on.
• The saturated transistor Q1 causes a voltage of
approximately zero volts to appear at the common
node of RA and RB.
• Thus C begins to discharge through RB and the
collector of Q1.
• The voltage vC decreases exponentially with a time
constant CRB toward 0 V.
• When vC reaches the threshold of comparator 2, VTL,
the output of comparator 2, goes high and sets the
flip-flop. Dr. Tanmay Dubey, MIET Meerut 13
Astable Multivibrator Using the
555 IC
• The output vO then goes high, and Q’ goes low,
turning off Q1.
• Capacitor C begins to charge through the series
equivalent of RA and RB, and its voltage rises
exponentially toward VCC with a time constant
C(RA + RB).
• This rise continues until vC reaches VTH, at which time
the output of comparator 1 goes high, resetting the
flip-flop, and the cycle continues.

Dr. Tanmay Dubey, MIET Meerut 14

Astable Multivibrator Using the
555 IC
• From the description above we see that the circuit of
Fig. (a) oscillates and produces a square waveform at
the output.
• The frequency of oscillation can be determined as
follows.
• Reference to Fig. (b) indicates that the output will be
high during the interval TH , in which vC rises from VTL
to VTH . The exponential rise of vC can be described by

• where t = 0 is the instant at which the interval TH

begins. Substituting vC = VTH = 2/3VCC at t = TH and VTL
= 1/3VCC results in
Dr. Tanmay Dubey, MIET Meerut 15
Astable Multivibrator Using the
555 IC
• Also, vO will be low during the interval TL, in which vC
falls toward zero, from VTH to VTL.
• The exponential fall of vC can be described by

• where we have taken t = 0 as the beginning of the

interval TL.
• Substituting vC = VTL = 1/3VCC at t = TL and VTH =
2/3VCC results in

Dr. Tanmay Dubey, MIET Meerut 16

Astable Multivibrator Using the
555 IC
• The period T of the output square wave is

• Also, the duty cycle of the output square wave can be

found as

• Note that the duty cycle will always be greater than

0.5 (50%); it approaches 0.5 if RA is selected to be
much smaller than RB (unfortunately, at the expense
of increased supply current).

Dr. Tanmay Dubey, MIET Meerut 17

Application of Monostable
Multivibrator
• Missing pulse detector
• Linear ramp generator
• Frequency divider
• Pulse width modulator

Dr. Tanmay Dubey, MIET Meerut 18

Missing pulse detector

Dr. Tanmay Dubey, MIET Meerut 19

Linear ramp generator
• The resistor R of the monostable circuit is replaced
by a constant current source.
• The capacitor is charged linearly by the constant
current sourced formed by the transistor Q3.
• The voltage Vc can be written as
t
1
VC  idt
C0

• Where i is the current supplied by the constant

current source.
• The output is taken across the capacitor.
• The capacitor discharges as soon as its voltage
reaches 2/3Vcc which is threshold voltage of upper
comparator.
• The circuit output remains zero till another trigger is
Dr. Tanmay Dubey, MIET Meerut 20
applied.
Frequency divider
• Figure shows a monostable multivibrator circuit
which is used as frequency divider by being
continuously triggered.
• This trigger signal is the input of the circuit, this signal
frequency is divided based on the time period of the
circuit.
• In general, time period of the circuit is adjusted to be
longer [time period is longer means, frequency is less
(f= 1/T)].

Dr. Tanmay Dubey, MIET Meerut 21

Frequency divider
• The monostable multivibrator will be triggered by
the first negative going edge of the square wave
input.
• However the output will remain HIGH (because of
greater timing interval) for next negative going edge
of the input square wave.
• The mono-shot will however be triggered on the
third negative going input.
• Depending on the choice of the time delay, the
output can be made fractions of the frequency of
the input triggering square wave.

Dr. Tanmay Dubey, MIET Meerut 22

Example
Ques: Calculate (a) thigh (b) tLow and (c) the free running
frequency for the timer circuit of figure shown.

Dr. Tanmay Dubey, MIET Meerut 23

Example
Ques: Calculate the timing interval of monostable multivibrator if RA = 10 kΩ and
C =0.1 µF.
Solution:

Dr. Tanmay Dubey, MIET Meerut 24

 Voltage-Controlled Oscillator
(VCO) IC 566
• In some applications, such as frequency
modulation(FM), tone generators, and frequency
shift keying (FSK), the frequency needs to be
controlled by means of an input voltage called
control voltage.
• This function is achieved in the Voltage-
Controlled Oscillator (VCO), also called a voltage-
to-frequency converter.
• A typical example is the Signetics NE/SE 566
VCO, which provides simultaneous square wave
and triangular wave outputs as a function of
input voltage.

Dr. Tanmay Dubey, MIET Meerut 25

 Voltage-Controlled Oscillator
(VCO) IC 566
• The frequency of oscillation is determined by an
external resistor R1, capacitor C1, and the
voltage Vc applied to the control terminal 5.
• The triangular wave is generated by alternately
charging the external capacitor C1 by one
current source and then linearly discharging it by
another.
• The charge discharge levels are determined by
Schmitt trigger action. The Schmitt trigger also
provides the square wave output.
• Both the output waveforms are buffered so that
the output impedance of each is 50 Ω.
• The typical amplitude of the triangular wave is
2.4 Vpp and that of the square wave is 5.4 Vpp.
Dr. Tanmay Dubey, MIET Meerut 26
 Voltage-Controlled Oscillator
(VCO) IC 566
• Figure (c) is a typical connection diagram.
• In this arrangement, the R1C1 combination
determines the free-running frequency, and the
control voltage Vc at terminal 5 is set by the
voltage divider formed with R2 and R3.
• The initial voltage Vc at terminal 5 must be in the
range
3
(V ) VC V
4

• Where +V is the total supply voltage. The

modulating signal is ac coupled with the
capacitor C and must be <3 Vpp.

Dr. Tanmay Dubey, MIET Meerut 27

 Voltage-Controlled Oscillator
(VCO) IC 566
• The frequency of the output waveforms is approximated by
2(V  VC )
fo 
R1C1 (V )

• where R1 should be in the range 2kΩ<R1<20kΩ.

• For a fixed Vc and constant C1, the frequency fo can be
varied over a 10:1 frequency range by the choice of R1
between2 kΩ and 20 kΩ.
• Similarly, for a constant R1C1 product, the frequency fo can
be modulated over a 10: I range by the control voltage Vc.
• In either case the maximum output frequency is I MHz.
• A small capacitor of 0.001 µF should be connected
between pins 5 and 6 to eliminate possible oscillations in
the control current source.
Dr. Tanmay Dubey, MIET Meerut 28
 Voltage-Controlled Oscillator
(VCO) IC 566
• If the VCO is to be used to drive standard logic circuitry, a
dual supply of ±5V is recommended so that the square
wave output has the proper dc levels for logic circuitry.
• The VCO is commonly used in converting low-frequency
signals such as electroencephalograms (EEG) or
electrocardiograms (EKG) into an audio-frequency range.
• These audio signals can then be transmitted over
telephone lines or two-way radio communication for
diagnostic purposes or can be recorded on a magnetic
tape for documentation or further reference.

Dr. Tanmay Dubey, MIET Meerut 29

Example
Ques: In the circuit of Figure, +V = 12 V, R2 = 1.5 kΩ, R1 =
R3 = 10 kΩ and C1 = 0.001 uF.
a. Determine the nominal frequency of the output
waveforms.
b. Compute the modulation in the output frequencies if Vc
is varied between 9.5 V and 11.5 V.
c. Draw the square wave output waveform if the
modulating input is a sine wave.

Dr. Tanmay Dubey, MIET Meerut 30

Example
Solution:

Dr. Tanmay Dubey, MIET Meerut 31

Example
Solution:
c. During the positive half-cycle of the sine wave input, the
control voltage Vc will increase. Therefore, the frequency of
the output waveform will decrease and the time period will
increase. Exactly the opposite action will take place during
the negative half-cycle of the input, as shown in Figure

Dr. Tanmay Dubey, MIET Meerut 32

 Phase-Locked Loops
• Although the evolution of the phase-locked loop began in the early 1930s. Its cost
overweighed its advantages at first.
• With the rapid development of integrated-circuit technology. however. the phase-
locked loop has emerged as one of the fundamental building blocks in electronics
technology.
• The phase-locked loop principle has been used in applications such as FM
(frequency modulation) stereo decoders, motor speed controls, tracking filters,
frequency synthesized transmitters and receivers, FM demodulators, frequency
shift keying (FSK) decoders, and a generation of local oscillator frequencies in
TV and in FM tuners.
• Today the phase-locked loop is even available as a single package, typical
examples of which include the Signet ICs SE/NE 560 series (the 560, 561, 562,
564, 565, and 567).
• However, for more economical operation, discrete ICs can be used to construct a
phase-locked loop. Dr. Tanmay Dubey, MIET Meerut 33
 Operating Principles
• Figure shows the phase-locked loop
(PLL) in its basic form.
• As illustrated in this figure, the phase-
locked loop consists of
• a phase detector,
• a low- pass filter, and
• a voltage-controlled oscillator.

Dr. Tanmay Dubey, MIET Meerut 34

 Operating Principles
• The phase detector, or comparator compares
the input frequency fIN with the feedback
frequency fout.
• The output of the phase detector is
proportional to the phase difference
between fIN and fout.
• The output voltage of a phase detector is a
dc voltage and therefore is often referred to
as the error voltage.
• The output of the phase detector is then
applied to the low-pass filter, which removes
the high-frequency noise and produces a dc
level.
• This dc level, in turn, is the input to tne
voltage-controlled oscillator (VCO). Dr. Tanmay Dubey, MIET Meerut 35
 Operating Principles
• The filter also helps in establishing the
dynamic characteristics of the PLL circuit.
• The output frequency of the VCOs directly
proportional to the input dc level.
• The VCO frequency is compared with the
input frequencies and adjusted until it is
equal to the input frequencies.
• In short, the phase-locked loop goes
through three states:
• free-running,
• capture, and
• phase lock.

Dr. Tanmay Dubey, MIET Meerut 36

 Operating Principles
• Before the input is applied, the phase-locked
loop is in the free-running state.
• Once the input frequency is applied, the VCO
frequency starts to change and the phase-
locked loop is said to be in the capture mode.
• The VCO frequency continues to change until
it equals the input frequency, and the phase-
locked loop is then in the phase-locked state.
• When phase locked, the loop tracks any
change in the input frequency through its
repetitive action.

Dr. Tanmay Dubey, MIET Meerut 37

 Phase detector
• The phase detector compares the input frequency and the VCO frequency and
generates a dc voltage that is proportional to the phase difference between the
two frequencies.
• Depending on whether the analog or digital phase detector is used, the PLL is
called either
• Analog or
• Digital type.
• Even though most of the monolithic PLL integrated circuits use analog phase
detectors, the majority of discrete phase detectors in use are of the digital type
mainly because of its simplicity.

Dr. Tanmay Dubey, MIET Meerut 38

Analog Phase Detector
• Figure 1 shows a switch type phase detector.
• An electronic switch S is opened and closed by signal
coming from VCO (normally a square wave).
• The input signal V, assumed to be in phase (ɸ= 0°) as
shown in Fig. 2, with VCO output Vo.
• Since the switch S is closed only when VCO output is
positive, otherwise it is open.
• Let us see the output of phase detector at different
phase angles of input signals.
• When ɸ = 0, i.e. when the input signal Vin is in phase
with VCO output Vo, the output wave Ve will be
positive half sinusoids (shaded portion).
• When 90°, the output waveform V, contains half
portion of negative cycle and half portion positive
Dr. Tanmay Dubey, MIET Meerut 39
cycle.
Analog Phase Detector
• When ɸ=180°, the output waveform contains
negative half sinusoids.
• The average output voltage (error voltage) at
different phase angles of input signals are shown in
figures by dotted line.
• It may be seen that the error voltage is zero when
the phase shift between two inputs (Vin and Vout )
is 90°. This is a perfect lock condition.
• For phase shifts 0° and 180° the error voltage is
positive and negative, respectively.

Dr. Tanmay Dubey, MIET Meerut 40

Analog Phase Detector

Dr. Tanmay Dubey, MIET Meerut 41

Analog Phase Detector

Dr. Tanmay Dubey, MIET Meerut 42

Digital Phase Detector
• Examples of digital phase detectors are
1. Exclusive-OR phase detector 2.
2. Edge-triggered phase detector
3. 3. Monolithic phase detector (such as type 4044)

Dr. Tanmay Dubey, MIET Meerut 43

Exclusive-OR phase detector
• Figure (a) shows the exclusive-OR phase detector
that uses an exclusive-OR gate such as CMOS type
4070.
• The output of the exclusive-OR gate is high only
when fIN or fout is high, as shown in Figure 9-26(b).
• fIN is leading fout by ɸ degrees; that is, the phase
difference between fIN and fout is ɸ degrees.
• The dc output voltage of the Exclusive-OR phase
detector is a function of the phase difference
between its two inputs.

(a)
Dr. Tanmay Dubey, MIET Meerut 44
Exclusive-OR phase detector
• Figure (c) shows dc output voltage as a function of
the phase difference between fIN and fout.
• This graph indicates that the maximum dc output
voltage occurs when the phase difference is π
radians or 180°.
• The slope of the curve between 0 and π radians is
the conversion gain kp of the phase detector.
• For example if the exclusive-OR gate uses a supply
voltage Vcc =5V, the conversion gain kp is
V 5V
k p  CC  1.59 V / rad
 

Dr. Tanmay Dubey, MIET Meerut 45

Edge-triggered phase detector,
• The exclusive-OR type of phase detector is generally
used if the fIN and fout are square waves.
• The edge-triggered phase detector, on the other
hand, is preferred if the fIN and fout are pulse
waveforms with less than 50% duty cycles.
• Figure (a) shows the edge-triggered type of phase
detector using an R- S (reset-set) flip-flop.
• The R-S flip-flop, in turn, is formed from a pair of
cross-coupled NOR gates, such as the CD4001.
• The R-S flip-flop is triggered; that is, the output of
the detector changes its logic state on the positive
(leading) edge of the inputs fIN and fOUT.

Dr. Tanmay Dubey, MIET Meerut 46

Edge-triggered phase detector,
• The advantages of the edge-triggered phase
detector over the exclusive-OR type of detector are
(1) The dc output voltage is linear over 2π radians or
360°, as opposed to π radians or 180° in the case
of the exclusive-OR detector, and
(2) The edge-triggered detector also exhibits better
capture, tracking, and locking characteristics than
the exclusive-OR detector. However, both types of
detectors are sensitive to harmonics of the input
signal and changes in the duty cycles of fin and fout

Dr. Tanmay Dubey, MIET Meerut 47

Low-pass filter
• The second block shown in the PLL block diagram is
a low pass filter.
• The function of the low-pass filter is to remove the
high-frequency components in the output of the
phase detector and to remove high-frequency noise.
• More important, the low pass filter controls the
dynamic characteristics of the phase-locked loop.
• These characteristics include
• Capture range,
• Lock ranges,
• Bandwidth, and
• Transient response.

Dr. Tanmay Dubey, MIET Meerut 48

Low-pass filter
• The lock range is defined as the range of frequencies over which the PLL system
follows the changes in the input frequency fin.
• An equivalent term for lock range is tracking range.
• On the other hand, the Capture range is the frequency range in which the PLL
acquires phase lock.
• Obviously, the capture range is always smaller than the lock range.
• As the filter bandwidth is reduced, its response time increases. However, reduced
bandwidth reduces the capture range of the PLL.
• Nevertheless, reduced bandwidth helps to keep the loop in lock through
momentary losses of signal and also minimizes noise.

Dr. Tanmay Dubey, MIET Meerut 49

 Voltage-controlled oscillator
• The third section of the PLL is the voltage-controlled
oscillator.
• The VCO generates an output frequency that is
directly proportional to its input voltage.

Dr. Tanmay Dubey, MIET Meerut 50

 Monolithic Phase-Locked Loops
(PLL IC)
• The Signetics SE/NE 560 series is monolithic phase-
locked loops.
• The SE/NE 560, 561, 562, 564, 565, and 567 differ
mainly in operating frequency range, power supply
requirements, and frequency and bandwidth
adjustment ranges.
• The device is available as a 14-pin DIP package and
as a 10-pin metal can package.
• The important electrical characteristics of the 565
PLL are:

Dr. Tanmay Dubey, MIET Meerut 51

 Monolithic Phase-Locked Loops
(PLL IC)
The important electrical characteristics of the 565 PLL
are:
• Operating frequency range: 0.001 Hz to 500 kHz
• Operating voltage range: ±6 to ± 12 V
• Input level required for tracking: 10 mV rms
minimum to 3 V peak-to- peak maximum.
• Input impedance: 10 kΩ typically
• Output sink current: I mA, typically
• Output source current: 10 mA, typically
• Drift in VCO center frequency (fouT) with
temperature: 300 ppm/°C, typically

Dr. Tanmay Dubey, MIET Meerut 52

 Monolithic Phase-Locked Loops
(PLL IC)
• Drift in VCO center frequency with supply voltage:
1.5%/V maximum
• Triangle wave amplitude: typically 2.4 Vpp at ±6V.
• Square wave amplitude: typically 5.4 Vpp at ±6V.
• Bandwidth adjustment range: < ± I to > ± 60%

Dr. Tanmay Dubey, MIET Meerut 53

 Monolithic Phase-Locked Loops
(PLL IC)
• The center frequency of the PLL is determined by the free-
running frequency of the VCO, which is given by the
equation 1.2
f out  Hz
4 R1C1

• Where R1 and C1 are an external resistor and a capacitor

connected to pins 8 and 9, respectively.
• The VCO free-running frequency f OUT is adjusted externally
with R1 and C1 to be at the center of the input frequency
range.
• Although C1 can be any value, R1 must have a value between
2kΩ and 20 kΩ.
• A capacitor C2 connected between pin 7 and the positive
supply (pin 10) forms a first-order low-pass filter with an
internal resistance of 3.6 k.
• The filter capacitor C2 should be large enough to eliminate
variations in the demodulated output voltage at pin 7 in
Dr. Tanmay Dubey, MIET Meerut 54
order to stabilize the VCO frequency.
 Monolithic Phase-Locked Loops
(PLL IC)
• The 565 PLL can lock to and track an input signal
over typically ±60% bandwidth with respect to
fout as the center frequency.
• The lock range fL and capture range fc of the PLL
are given by the following equations:
8f
f L  out Hz
V

• where fOUT= free-running frequency of VCO (Hz)

V = (+V) -(-V)(volts) and 1
 fL  2
fC  3  Hz
 2 (3.6)(10 )C2 

• where C2 is in farads.
Dr. Tanmay Dubey, MIET Meerut 55
 Monolithic Phase-Locked Loops
(PLL IC)
• The lock range usually increases with an
increase in input voltage but decreases with an
increase in supply voltages.
• Pins 2 and 3 are the input terminals of the 565
PLL, and an input signal can be direct-coupled,
provided that there no dc voltage difference
between the pins and the dc resistances seen
from pin 2 and 3 are equal.
• A Short between pins 4 and 5 connects the VCO
output fout to the phase comparator and enables
the comparator to compare fout with the input
signal fIN.

Dr. Tanmay Dubey, MIET Meerut 56

 Monolithic Phase-Locked Loops
(PLL IC)
• The lock range usually increases with an
increase in input voltage but decreases with an
increase in supply voltages.
• Pins 2 and 3 are the input terminals of the 565
PLL, and an input signal can be direct-coupled,
provided that there no dc voltage difference
between the pins and the dc resistances seen
from pin 2 and 3 are equal.
• A Short between pins 4 and 5 connects the VCO
output fout to the phase comparator and enables
the comparator to compare fout with the input
signal fIN.

Dr. Tanmay Dubey, MIET Meerut 57

 Example
Ques: Referring to the circuit shown, determine
the free running frequency fout , the lock range fL,
and the capture range fC.

Dr. Tanmay Dubey, MIET Meerut 58

 PLL Applications
• PLL is a versatile device. It has a numerous applications. PLL is used for the main
applications are listed below.
1. Frequency divider
2. Frequency multiplier
3. Frequency synthesizer
4. AM detector
5. FM detector
6. FSK demodulator

Dr. Tanmay Dubey, MIET Meerut 59

Frequency Multiplier
• Figure shows the block diagram for a
frequency multiplier using PLL 565.
• Here a divide by network is inserted between
VCO output (pin 4) and phase comparator
input (pin 5)
• Since the output of the divider is locked to
the input frequency fs, the VCO is running at a
multiple of the input frequency.
• Therefore in the locked state, the VCO output
frequency fo, is given by
f o  Nf s
• where N is the multiplication factor can be
obtained by selecting a proper scaling factor
N of the counter. Dr. Tanmay Dubey, MIET Meerut 60
Frequency Synthesizer
• The PLL can be used as the basis for frequency
synthesizer that can produce a precise series
frequencies that are divided from a stable crystal
controlled oscillator.
• Fig. shows the block diagram of a frequency,
synthesizer.
• It is similar to frequency multiplier circuit except
that divided by M network is added at the input
of the phase locked loop.
• The frequency of the crystal oscillator is divided
by an integer factor M by divider network to a
produce a frequency fosc/M, where fosc is the
frequency of the crystal oscillator.
• The VCO frequency fs is similarly divided by factor
N by divider network to given frequency equal to
f/N. Dr. Tanmay Dubey, MIET Meerut 61
Frequency Synthesizer
• When the PLL is locked.
f osc fo

M N
N
f o  f osc
M
• By adjusting divider counts to desired values
large number of frequencies can be
produced, all derived from the crystal
oscillator.

Dr. Tanmay Dubey, MIET Meerut 62

Frequency Translation
• The frequency translation means shifting the
frequency of an oscillator by a small factor.
• Fig. shows the block diagram for frequency
translator using PLL.
• It consist of mixer, low pass filter and PLL.
• The input frequency fs which has to be shifted
is applied to the mixer.
• Another input to the mixer is the output
voltage of VCO, fo.
• Therefore, the output of mixer contains the
sum and difference signal (fo±fs).
• The low pass filter connected at the output of
mixer rejects the (fo+fs) signal and gives only
(fo-fs ) signal at the output. Dr. Tanmay Dubey, MIET Meerut 63
Frequency Translation
• The (fo-fs ) signal is applied to the phase
detector.
• Another input for phase detector is the offset
frequency f1.
• In the locked mode, the VCO output
frequency is adjusted to make two input
frequencies of phase detector equal. This
gives f o  f s  f1
f o  f1  f s

• By adjusting offset frequency we can shift the

frequency of the oscillator to the desired
value.

Dr. Tanmay Dubey, MIET Meerut 64

FM demodulator
• The PLL can be used as an FM detector of
demodulator.
• When the PLL is locked in on the FM signal, the
VCO frequency follows the instantaneous
frequency of the FM signal and the error
voltage or VCO control voltage is proportional
to the deviation from the center frequency.
• Therefore, the ac component of error voltage or
control voltage of VCO will represent a true
replica of the modulating voltage that is applied
to the FM carrier at the transmitter.
• The faithful reproduction of modulating voltage
depends on the linearity between the
instantaneous frequency deviation and the
control voltage of VCO. Dr. Tanmay Dubey, MIET Meerut 65
FM demodulator
• It is also importance to note that the FM
frequency deviation and the modulating
frequency should remain in the locking range of
PLL to get the faithful replica of the modulating
signal.
• If the product of the modulation frequency fm
and the frequency deviation exceeds the Δfc2
the VCU will not be able to follow the
instantaneous frequency variations of the FM
signal.

Dr. Tanmay Dubey, MIET Meerut 66

Frequency Shift Keying (FSK)
Demodulator
• In digital data communication, binary data is
transmitted by means of a carrier frequency.
• It uses two different carrier frequencies for
logic-1 and logic-0 of binary digital signal.
• This type of data transmission is called
frequency shift keying (FSK).
• In this data transmission, on the receiving end,
two carrier frequencies are converted into 1
and 0 to get the original binary data.
• This process is called as FSK demodulation.
• The PLL can be used as a FSK demodulator as
shown in the Fig.

Dr. Tanmay Dubey, MIET Meerut 67

Frequency Shift Keying (FSK)
Demodulator
• It is similar to the PLL demodulator for analog
FM signals except for the addition of a
comparator to produce reconstructed digital
output signal.
• Let us consider that there are the frequencies,
one frequency (f1) is represented as "0" and
other frequency (f2), is represented as "1".
• If the PLL remain is locked into the FSK signal at
both f1 and f2.

Dr. Tanmay Dubey, MIET Meerut 68

Frequency Shift Keying (FSK)
Demodulator
• The VCO control voltage which is also supplied to
the comparator will be given as
(f  f )
VC1  1 o
KV
( f  fo )
VC 2  2
KV

• where KV is the voltage to frequency transfer

coefficient of the VCO.
• The difference between the two control voltage
levels will be ΔVc= (f2 –f1)/KV.
• The reference voltage for the comparator is
desired from the additional low pass filter and it
is adjusted midway between VC1 and VC2.
• Therefore, for VC1 and VC2 comparator gives
output “0” and “1" respectively. Dr. Tanmay Dubey, MIET Meerut 69
AM Detection
• The PLL is locked to the carrier frequency of the
incoming AM signal.
• Once locked the output frequency of VCO is same as
the carrier frequency, but it is in unmodulated form.
• The modulated signal with 90° phase shift and
unmodulated carrier from output of PLL are fed to the
multiplier are in same phase.
• Therefore, the output of the multiplier contains both
the sum and the difference signals.
• The low pass filter connected at the output of the
multiplier rejects high frequency components gives
demodulated output.
• As PLL follows the input frequencies with high
accuracy, a PLL AM detector exhibits high degree of
selectivity and noise immunity which is not possible
with conventional peak detector type AM modulators.
Dr. Tanmay Dubey, MIET Meerut 70
Example
Ques: A PLL has free running frequency of 500 kHz and bandwidth of the low pass
filter is 10 kHz. Will the loop acquire lock for input signal of 600 kHz? Justify answer.
Assume that detector produces sum and difference frequency components.

Dr. Tanmay Dubey, MIET Meerut 71

Example
Ques: Input to phased locked loop is having 2 Hz rate of variation. Design phase
locked loop for 10 kHz centre frequency. Find out capture range considering the
frequency deviation rate as given above. Find lock range also. Write values of
component clearly in the circuit diagram.

Dr. Tanmay Dubey, MIET Meerut 72

Example
Ques: Free running frequency is 100 kHz. Supply voltage is ±6 V. Demodulation
capacitor is 1 µF. Find out lock and capture frequencies and range of the PLL
employing LM 565. Design components of this PLL for given free running frequency.

Dr. Tanmay Dubey, MIET Meerut 73

Example
Ques: Using a 680 pF capacitor, design the astable circuit of using 555 timer to
obtain a square wave with a 50 kHz frequency and a 75% duty cycle. Specify the
values of RA and RB.

Dr. Tanmay Dubey, MIET Meerut 74