BANGALORE INSTITUTE OF TECHNOLOGY

Advanced Embedded Systems

(20EVE13)

Course Handling Faculty: Keshava A

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What are the ARM® Cortex®-M Processors?

 The Cortex® - M3 and Cortex® - M4 Processors
• Designed by ARM®
• The Cortex-M3 processor was the first of the Cortex generation of processors,
released by ARM in 2005 (silicon products released in 2006).
• The Cortex-M4 was released in 2010.
• Use a 32-bit architecture.
• Internal registers in the register bank, the data path, and bus interfaces are all
32 bits wide.
• The Instruction Set Architecture (ISA) in the Cortex-M processors is called
the Thumb® ISA and is based on Thumb-2 Technology which supports a
mixture of 16-bit and 32-bit instructions.

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Contd..,
 The Cortex® - M3 and Cortex® - M4 Processors have
• Three-stage pipeline design
• Harvard bus architecture with unified memory space: instructions and data use
the same address space
• 32-bit addressing, supporting 4GB of memory space
• On-chip bus interfaces based on ARM AMBA® (Advanced Microcontroller
Bus Architecture) Technology, which allow pipelined bus operations for
higher throughput
• An interrupt controller called NVIC (Nested Vectored Interrupt Controller)
supporting up to 240 interrupt requests and from 8 to 256 interrupt priority
levels (dependent on the actual device implementation)
• Support for various features for OS implementation such as a system tick
timer, shadowed stack pointer. 3

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Contd..,
• Sleep mode support and various low power features
• Support for an optional MPU ( Memory Protection Unit) to provide memory
protection features like programmable memory, or access permission control
• Support for bit-data accesses in two specific memory regions using a feature
called Bit Band
• The option of being used in single processor or multi-processor designs

 The ISA used in Cortex-M3 and Cortex-M4 processors provides a wide range
of instructions:
• General data processing, including hardware divide instructions
• Memory access instructions supporting 8-bit, 16-bit, 32-bit, and 64-bit data, as
well as instructions for transferring multiple 32-bit data
• Instructions for bit field processing 4

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Contd..,
• Multiply Accumulate (MAC) and saturate instructions
• Instructions for branches, conditional branches and function calls
• Instructions for system control, OS support, etc.

 In addition, the Cortex-M4 processor also supports:

• Single Instruction Multiple Data (SIMD) operations
• Additional fast MAC and Multiply instructions
• Saturating arithmetic instructions
• Optional floating point instructions (single precision)

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Contd..,
• Both the Cortex-M3 and Cortex-M4 processors are widely used in modern
microcontroller products, as well as other specialized silicon designs such as
System on Chips (SoC) and Application Specific Standard Products (ASSP).
• In general, the ARM Cortex-M processors are regarded as RISC processors.
• There are a lot of similarities between the Cortex-M3 and Cortex-M4
processors.
 Most of the instructions are available on both processors, and the processors
have the same programmer’s model for NVIC, MPU, etc.
• There are some differences in their internal designs, which allow the Cortex-
M4 processor to deliver higher performance in DSP applications, and to
support floating point operations.
• As a result, some of the instructions available on both processors can be
executed in fewer clock cycles on the Cortex-M4. 6

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The Cortex®-M Processor Family

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Differences between a processor and a microcontroller

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ARM® and the microcontroller vendors

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Selecting Cortex®-M3 and Cortex®-M4 Microcontrollers

• Peripherals and interface features
• Memory size requirements of the application
• Low power requirements
• Performance and maximum frequency
• Chip package
• Operational conditions (voltage, temperature, electromagnetic interference)
• Cost and availability
• Software development tool support and development kits
• Future upgradability
• Firmware packages and firmware security
• Availability of application notes, design examples, and support

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Advantages of the Cortex®-M Processors

• Low power
 Relatively small
 Power consumption of less than 200µA/MHz, some of them well under
100µA/MHz
 Support for sleep mode features and can be used with various advanced ultra-
low power design technologies
• Performance
• Energy efficiency
• Code density
• Interrupts
• Ease of use, C friendly
• Scalability
• Debug features 11

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Contd..,
• OS support
• Versatile system features
 Bit band feature, Memory Protection Unit (MPU)
• Software portability and reusability
• Choices (devices, tools, OS, etc.)

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Applications of the ARM Cortex®-M Processors

• Microcontrollers
• Automotive
• Data communication – Bluetooth, ZigBee
• Industrial control
• Consumer products
• Systems-on-Chips (SoC)
• Mixed signal designs

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ARM® Processor Evolution

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Architecture Versions and Thumb® ISA

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Contd..,

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The Thumb-2 Technology and Instruction Set Architecture

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Processor Naming
• Traditionally, ARM used a numbering scheme to name processors.
• In the early days (the 1990s), suffixes were also used to indicate features on the
processors.
• For example, with the ARM7TDMI processor, the T indicates Thumb instruction support,
D indicates JTAG debugging, M indicates fast multiplier, and I indicates an embedded
ICE module.
• Subsequently, it was decided that these features should become standard features of future
ARM processors; therefore, these suffixes are no longer added to the new processor
family names.
• Instead, variations on memory interface, cache, and tightly coupled memory (TCM) have
created a new scheme for processor naming.
• For example, ARM processors with cache and MMUs are now given the suffix “26” or
“36,” whereas processors with MPUs are given the suffix “46” (e.g.,RM946E-S).
• In addition, other suffixes are added to indicate synthesizable2 (S) and Jazelle (J)
technology. 18

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Contd..,

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Contd..,

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A simplified view of the Cortex-M3

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Registers

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Special Registers

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Operation modes
• The Cortex-M3 processor has two modes and two privilege levels.
• The operation modes (thread mode and handler mode) determine whether the processor is
running a normal program or running an exception handler like an interrupt handler or system
exception handler.
• The privilege levels (privileged level and user level) provide a mechanism for safeguarding
memory accesses to critical regions as well as providing a basic security model.

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The built-in Nested Vectored Interrupt Controller
• It provides number of features as follows:
 Nested interrupt support
 Vectored interrupt support
 Dynamic priority changes support
 Reduction of interrupt latency
 Interrupt masking

Nested interrupt support

 All the external interrupts and most of the system exceptions can be programmed to
different priority levels.
 When an interrupt occurs, the NVIC compares the priority of this interrupt to the current
running priority level.
 If the priority of the new interrupt is higher than the current level, the interrupt handler of
the new interrupt will override the current running task.
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Contd..,
Vectored interrupt support
 When an interrupt is accepted, the starting address of the interrupt service routine (ISR) is
located from a vector table in memory.
 There is no need to use software to determine and branch to the starting address of the ISR.
 Thus, it takes less time to process the interrupt request.

Dynamic priority changes support

 Priority levels of interrupts can be changed by software during run time.
 Interrupts that are being serviced are blocked from further activation until the ISR is
completed, so their priority can be changed without risk of accidental reentry.

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Contd..,
Reduction of interrupt latency
 The Cortex-M3 processor also includes a number of advanced features to lower the
interrupt latency.
 These include automatic saving and restoring some register contents, reducing delay in
switching from one ISR to another, and handling of late arrival interrupts.

Interrupt masking
 Interrupts and system exceptions can be masked based on their priority level or masked
completely using the interrupt masking registers BASEPRI, PRIMASK, and
FAULTMASK.
 They can be used to ensure that time-critical tasks can be finished on time without being
interrupted.

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The Memory Map
• The Cortex-M3 has a predefined memory map
• This allows the built-in peripherals, such as the
interrupt controller and the debug components,
to be accessed by simple memory access
instructions.
• Thus, most system features are accessible in C
program code.
• The predefined memory map also allows the
Cortex-M3 processor to be highly optimized
for speed and ease of integration in system-on-
a-chip (SoC) designs.
• Overall, the 4 GB memory space can be
divided into ranges as shown in figure.
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Contd..,
• The Cortex-M3 design has an internal bus infrastructure optimized for this memory
usage.
• In addition, the design allows these regions to be used differently.
• For example, data memory can still be put into the CODE region, and program code
can be executed from an external Random Access Memory (RAM) region.
• The system-level memory region contains the interrupt controller and the debug
components. These devices have fixed addresses.
• By having fixed addresses for these peripherals, you can port applications between
different Cortex-M3 products much more easily.

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The Bus Interface
• There are several bus interfaces on the Cortex-M3 processor. They allow the Cortex-
M3 to carry instruction fetches and data accesses at the same time.
• The main bus interfaces are as follows:
 Code memory bus
 The code memory region access is carried out on the code memory buses, which
physically consist of two buses, one called I-Code and other called D-Code. These are
optimized for instruction fetches for best instruction execution speed.
 System bus
 The system bus is used to access memory and peripherals. This provides access to the
Static Random Access Memory (SRAM), peripherals, external RAM, external
devices, and part of the system-level memory regions.
 Private peripheral bus
 The private peripheral bus provides access to a part of the system-level memory
dedicated to private peripherals, such as debugging components. 30

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The MPU
• The Cortex-M3 has an optional MPU.
• This unit allows access rules to be set up for privileged access and user program
access.
• When an access rule is violated, a fault exception is generated, and the fault exception
handler will be able to analyze the problem and correct it, if possible.
• The MPU can be used in various ways.
• In common scenarios, the OS can set up the MPU to protect data use by the OS kernel
and other privileged processes to be protected from untrusted user programs.
• The MPU can also be used to make memory regions read-only, to prevent accidental
erasing of data or to isolate memory regions between different tasks in a multitasking
system.
• Overall, it can help make embedded systems more robust and reliable.
• The MPU feature is optional and is determined during the implementation stage of the
microcontroller or SoC design. 31

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The Instruction Set
• The Cortex-M3 supports the Thumb-2 instruction set. This is one of the most
important features of the Cortex-M3 processor because it allows 32-bit instructions
and 16-bit instructions to be used together for high code density and high efficiency. It
is flexible and powerful yet easy to use.

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Contd..,
• With the introduction of the Thumb-2 instruction set, it is now possible to handle all
processing requirements in one operation state. There is no need to switch between the
two.
• In fact, the Cortex-M3 does not support the ARM code. Even interrupts are now
handled with the Thumb state.
• Since there is no need to switch between states, the Cortex-M3 processor has a
number of advantages over traditional ARM processors, such as:
 No state switching overhead, saving both execution time and instruction space.
 No need to separate ARM code and Thumb code source files, making software
development and maintenance easier.
 It’s easier to get the best efficiency and performance, in turn making it easier to write
software, because there is no need to worry about switching code between ARM and
Thumb to try to get the best density/performance.
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Contd..,
• The Cortex-M3 processor has a number of interesting and powerful instructions. Here are
a few examples:
 UFBX, BFI, and BFC: Bit field extract, insert, and clear instructions
 UDIV and SDIV: Unsigned and signed divide instructions
 WFE, WFI, and SEV: Wait-For-Event, Wait-For-Interrupts, and Send-Event; these allow
the processor to enter sleep mode and to handle task synchronization on multiprocessor
systems
 MSR and MRS: Move to special register from general-purpose register and move special
register to general-purpose register; for access to the special registers
• Since the Cortex-M3 processor supports the Thumb-2 instruction set only, existing
program code for ARM needs to be ported to the new architecture.
• Most C applications simply need to be recompiled using new compilers that support the
Cortex-M3.
• Some assembler codes need modification and porting to use the new architecture and the
new unified assembler framework. 34

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Contd..,
• Note that not all the instructions in the Thumb-2 instruction set are implemented on
the Cortex-M3.
• The ARMv7-M Architecture Application Level only requires a subset of the Thumb-2
instructions to be implemented.
• For example, coprocessor instructions are not supported on the Cortex- M3 (external
data processing engines can be added), and Single Instruction–Multiple Data (SIMD)
is not implemented on the Cortex-M3.
• In addition, a few Thumb instructions are not supported, such as Branch with Link and
Exchange (BLX) with immediate (used to switch processor state from Thumb to
ARM), a couple of change process state (CPS) instructions, and the SETEND (Set
Endian) instructions, which were introduced in architecture v6.

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Interrupts and Exceptions
• The Cortex-M3 processor implements a new exception model, introduced in the
ARMv7-M architecture. This exception model differs from the traditional ARM
exception model, enabling very efficient exception handling.
• It has a number of system exceptions plus a number of external Interrupt Request
(IRQs) (external interrupt inputs).
• There is no fast interrupt (FIQ) (fast interrupt in ARM7/ARM9/ARM10/ARM11) in
the Cortex-M3; however, interrupt priority handling and nested interrupt support are
now included in the interrupt architecture.
• Therefore, it is easy to set up a system that supports nested interrupts (a higher-priority
interrupt can override or preempt a lower-priority interrupt handler) and that behaves
just like the FIQ in traditional ARM processors.
• The interrupt features in the Cortex-M3 are implemented in the NVIC. Aside from
supporting external interrupts, the Cortex-M3 also supports a number of internal
exception sources, such as system fault handling. 36

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Contd..,

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Contd..,
Low Power and High Energy Efficiency
• The Cortex-M3 processor is designed with various features to allow designers to develop
low power and high energy efficient products.
• First, it has sleep mode and deep sleep mode supports, which can work with various
system-design methodologies to reduce power consumption during idle period.
• Second, its low gate count and design techniques reduce circuit activities in the processor
to allow active power to be reduced.
• In addition, since Cortex-M3 has high code density, it has lowered the program size
requirement.
• At the same time, it allows processing tasks to be completed in a short time, so that the
processor can return to sleep modes as soon as possible to cut down energy use.
• As a result, the energy efficiency of Cortex-M3 is better than many 8-bit or 16-bit
microcontrollers.
• Starting from Cortex-M3 revision 2, a new feature called Wakeup Interrupt Controller
(WIC) is available. 38

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Debugging Support
• The Cortex-M3 processor includes a number of debugging features, such as program
execution controls, including halting and stepping, instruction breakpoints, data
watchpoints, registers and memory accesses, profiling, and traces.
• The debugging hardware of the Cortex-M3 processor is based on the CoreSight™
architecture.
• Unlike traditional ARM processors, the CPU core itself does not have a Joint Test Action
Group (JTAG) interface.
• Instead, a debug interface module is decoupled from the core, and a bus interface called
the Debug Access Port (DAP) is provided at the core level.
• Through this bus interface, external debuggers can access control registers to debug
hardware as well as system memory, even when the processor is running.
• The control of this bus interface is carried out by a Debug Port (DP) device.
• The DPs currently available are the Serial-Wire JTAG Debug Port (SWJ-DP) (supports
the traditional JTAG protocol as well as the Serial-Wire protocol) or the SW-DP (supports
the Serial-Wire protocol only). 39

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Contd..,
• A JTAG-DP module from the ARM CoreSight product family can also be used. Chip
manufacturers can choose to attach one of these DP modules to provide the debug
interface.
• Chip manufacturers can also include an Embedded Trace Macrocell (ETM) to allow
instruction trace.
• Trace information is output via the Trace Port Interface Unit (TPIU), and the debug
host (usually a Personal Computer [PC]) can then collect the executed instruction
information via external trace-capturing hardware.
• Within the Cortex-M3 processor, a number of events can be used to trigger debug
actions.
• Debug events can be breakpoints, watchpoints, fault conditions, or external debugging
request input signals.
• When a debug event takes place, the Cortex-M3 processor can either enter halt mode
or execute the debug monitor exception handler. 40

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Contd..,
• The data watchpoint function is provided by a Data Watchpoint and Trace (DWT) unit
in the Cortex-M3 processor.
• This can be used to stop the processor (or trigger the debug monitor exception routine)
or to generate data trace information.
• When data trace is used, the traced data can be output via the TPIU.
• In addition to these basic debugging features, the Cortex-M3 processor also provides a
Flash Patch and Breakpoint (FPB) unit that can provide a simple breakpoint function
or remap an instruction access from Flash to a different location in SRAM.
• An Instrumentation Trace Macrocell (ITM) provides a new way for developers to
output data to a debugger.
• By writing data to register memory in the ITM, a debugger can collect the data via a
trace interface and display or process them.
• This method is easy to use and faster than JTAG output.
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Characteristics Summary
• High performance
• Advanced Interrupt-handling features
• Low power consumption
• System features
• Debug supports

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Registers
• The Cortex™-M3 processor has registers R0 through R15
and a number of special registers.
• R0 through R12 are general purpose, but some of the 16-bit
Thumb® instructions can only access R0 through R7 (low
registers), whereas 32-bit Thumb-2 instructions can access
all these registers.
• Special registers have predefined functions and can only be
accessed by special register access instructions.
General Purpose Registers R0 through R7
The R0 through R7 general purpose registers are also called low registers.
They can be accessed by all 16-bit Thumb instructions and all 32-bit
Thumb-2 instructions. They are all 32 bits; the reset value is unpredictable.
General Purpose Registers R8 through R12
The R8 through R12 registers are also called high registers. They are
accessible by all Thumb-2 instructions but not by all 16-bit Thumb
instructions. These registers are all 32 bits; the reset value is
unpredictable 43

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Contd..,
Stack Pointer R13
• R13 is the stack pointer (SP). In the Cortex-M3 processor, there are two SPs. This duality
allows two separate stack memories to be set up.
• When using the register name R13, you can only access the current SP; the other one is
inaccessible unless you use special instructions to move to special register from general-
purpose register (MSR) and move special register to general-purpose register (MRS).
• The two SPs are as follows:
 Main Stack Pointer (MSP) or SP_main in ARM documentation: This is the default SP; it is
used by the operating system (OS) kernel, exception handlers, and all application codes that
require privileged access.
 Process Stack Pointer (PSP) or SP_process in ARM documentation: This is used by the base-
level application code (when not running an exception handler).
• It is not necessary to use both SPs. Simple applications can rely purely on the MSP. The SPs
are used for accessing stack memory processes such as PUSH and POP.
PUSH {R0} ; R13=R13-4, then Memory[R13] = R0
POP {R0} ; R0 = Memory[R13], then R13 = R13 + 4 44

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Contd..,
subroutine_1
PUSH {R0-R7, R12, R14} ; Save registers
... ; Do your processing
POP {R0-R7, R12, R14} ; Restore registers
BX R14 ; Return to calling function
• Inside program code, both the MSP and the PSP can be
called R13/SP. However, you can access a particular one
using special register access instructions (MRS/MSR).
• The MSP, also called SP_main in ARM documentation, is
the default SP after power-up; it is used by kernel code and
exception handlers. The PSP, or SP_process in ARM
documentation, is typically used by thread processes in
system with embedded OS running.
• Because register PUSH and POP operations are always
word aligned, the SP/R13 bit 0 and bit 1 are hardwired to 0
and always read as zero (RAZ). 45

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Contd..,
Link Register R14
• R14 is the link register (LR). Inside an assembly program, you can write it as either R14 or
LR. LR is used to store the return program counter (PC) when a subroutine or function is
called—for example, when you’re using the branch and link (BL) instruction:
main ; Main program
...
BL function1 ; Call function1 using Branch with Link instruction.
; PC = function1 and
; LR = the next instruction in main
...
function1
... ; Program code for function 1
BX LR ; Return
• Despite the fact that bit 0 of the PC is always 0 (because instructions are word aligned or half
word aligned), the LR bit 0 is readable and writable.
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Contd..,
Program Counter R15
• R15 is the PC. You can access it in assembler code by either R15 or PC.
• Because of the pipelined nature of the Cortex-M3 processor, when you read this register, you
will find that the value is different than the location of the executing instruction, normally by
4.
0x1000 : MOV R0, PC ; R0 = 0x1004

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Program Status Registers
• The PSRs are subdivided into three status registers:
 Application Program Status register (APSR)
 Interrupt Program Status register (IPSR)
 Execution Program Status register (EPSR)
• The three PSRs can be accessed together or separately using the special register access
instructions MSR and MRS.
• When they are accessed as a collective item, the name xPSR is used.
• You can read the PSRs using the MRS instruction. You can also change the APSR using the
MSR instruction, but EPSR and IPSR are read-only.
MRS r0, APSR ; Read Flag state into R0
MRS r0, IPSR ; Read Exception/Interrupt state
MRS r0, EPSR ; Read Execution state
MSR APSR, r0 ; Write Flag state

MRS r0, PSR ; Read the combined program status word

MSR PSR, r0 ; Write combined program state word 48

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Contd..,

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Contd..,

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PRIMASK, FAULTMASK and BASEPRI Registers
• The PRIMASK, FAULTMASK, and BASEPRI registers are used to disable exceptions
• The PRIMASK and BASEPRI registers are useful for temporarily disabling interrupts in timing-
critical tasks.
• An OS could use FAULTMASK to temporarily disable fault handling when a task has crashed.

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Contd..,
x = __get_BASEPRI(); // Read BASEPRI register
x = __get_PRIMARK(); // Read PRIMASK register
x = __get_FAULTMASK(); // Read FAULTMASK register
__set_BASEPRI(x); // Set new value for BASEPRI
__set_PRIMASK(x); // Set new value for PRIMASK
__set_FAULTMASK(x); // Set new value for FAULTMASK
__disable_irq(); // Clear PRIMASK, enable IRQ
__enable_irq(); // Set PRIMASK, disable IRQ

MRS r0, BASEPRI ; Read BASEPRI register into R0

MRS r0, PRIMASK ; Read PRIMASK register into R0
MRS r0, FAULTMASK ; Read FAULTMASK register into R0
MSR BASEPRI, r0 ; Write R0 into BASEPRI register
MSR PRIMASK, r0 ; Write R0 into PRIMASK register
MSR FAULTMASK, r0 ; Write R0 into FAULTMASK register

• The PRIMASK, FAULTMASK, and BASEPRI registers cannot be set in the user access level.
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The Control Register
• The control register is used to define the privilege level and the SP selection. This register has
2 bits
CONTROL[1]
• In the Cortex-M3, the CONTROL[1] bit is always 0 in handler mode. However, in the thread
or base level, it can be either 0 or 1.
• This bit is writable only when the core is in thread mode and privileged.
• In the user state or handler mode, writing to this bit is not allowed. Aside from writing to this
register, another way to change this bit is to change bit 2 of the LR when in exception return.
CONTROL[0]
• The CONTROL[0] bit is writable only in a privileged state.
• Once it enters the user state, the only way to switch back to privileged is to trigger an interrupt
and change this in the exception handler.
x = __get_CONTROL(); // Read the current value of CONTROL
__set_CONTROL(x); // Set the CONTROL value to x
MRS r0, CONTROL ; Read CONTROL register into R0
MSR CONTROL, r0 ; Write R0 into CONTROL register 53

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Operation Mode

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Contd..,

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Exceptions and Interrupts

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Vector Tables

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Stack Memory Operations
Basic Operations of the stack

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Contd..,

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Contd..,

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Contd..,
Cortex-M3 Stack Implementation

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Contd..,
The Two-Stack Model in the Cortex-M3

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Contd..,
x = __get_MSP(); // Read the value of MSP
__set_MSP(x); // Set the value of MSP
x = __get_PSP(); // Read the value of PSP
__set_PSP(x); // Set the value of PSP

MRS R0, MSP ; Read Main Stack Pointer to R0

MSR MSP, R0 ; Write R0 to Main Stack Pointer
MRS R0, PSP ; Read Process Stack Pointer to R0
MSR PSP, R0 ; Write R0 to Process Stack Pointer

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Reset Sequence
• After the processor exits reset, it will read two words from memory (see Figure 3.18):
 Address 0x00000000: Starting value of R13 (the SP)
 Address 0x00000004: Reset vector (the starting address of program execution; LSB should be
set to 1 to indicate Thumb state)

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Contd..,

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