SPPU BE E&TC FDP

By Dr Vilas V Deotare
Prof. and Head E&TC
Nutan Maharashtra Institute of Engineering and Technology (NMIET)
 Unit 2
Digital Design and Issues
 Need of State Machines
1) In combinational circuits, Kmap is used to
minimize no of gates required to implement a
logic function.
2) In sequential Circuits, State machine plays
the same role :it minimizes no of flip flops.
 State Diagram
State name
Moore m/c

1) Behavior of a sequential circuits can

be described in different ways. The Output
simplest method uses pictorial
representation known as state
diagram.
2) In state diagram, the states of the
circuits are shown as nodes or circles
& the transitions between states are
Traditions
shown as arcs.
3) e.g. Consider the design of
sequential circuit with following
conditions State name
i) The circuit has single input W and
single output Z
Input
ii) If two successive clock pulses, I/P W
is 1 and then the O/P Z is 1.
Otherwise it is 0. Mealy m/c
Output
 Finite State Machines

• Finite State Machines (FSM) are

sequential circuit used in many Present Output
digital systems to control the State Moore M/C
behavior of systems and
dataflow paths. Examples of
FSM include control units and
sequencers Present
• The state machines are modeled State Output
Mealy M/C
using two basic types of
sequential networks- Mealy and
Input
Moore. In a Mealy machine, the
output depends on both the
present (current) state and the
present (current) inputs. In
Moore machine, the output
depends only on the present
state.
Moore and Mealy FSM
Moore state machine
State table
 VHDL Code for Moore FSM
entity simplefsm is
port(clock, reset: in std_logic;
w:in std_logic;
z:out std_logic);
end simplefsm;
architecture behave of simplefsm is
type state_values is(a, b, c);--define states
signal state: state_values;
--create signal that defines different states
begin
process(clock, reset)
begin
if(reset=‘1’) then state<=a;
else rising_edge(clock) then
case state is
when a=>
if w=‘1’ then state <=b;
end if;
when b=>
if w=‘1’ then state<=c;
end if;
when c=>
if w=1 then state<=c;
--else state<=a;
end if;
when others=> state<=a;
end case;
end if;
end process;
z<= ‘1’ when state =c else ‘0’;--output
end behave;
 Mealy FSM
• A general model of a Mealy sequential machine consists of a combinatorial
network, which generates the outputs and the next state, and a state register
which holds the present state as shown below. The state register is normally
modeled as D flip-flops. The state register must be sensitive to a clock edge. The
other block(s) can be modeled either using the always procedural block or a
mixture of the always procedural block and dataflow modeling statements; the
always procedural block will have to be sensitive to all inputs being read into the
block and must have all output defined for every branch in order to model it as a
combinatorial block.
• The two blocks Mealy machine fig 1 The Three block Moore machine fig2
Fig1. Fig2.
 Mealy Machine
VHDL Code for Mealy Machine:
library ieee;
ieee.std_logic_1164.all;
entity mealyfsm is
port( clock, reset, w: in std_logic;
z:out std_logic);
end mealyfsm;
architecture mealy_arch of mealyfsm is
type state_type is( a , b );
signal state: state_type;
begin
P0:process( reset, clock)
begin
if (reset=1) then
State<=a;
elseif rising_edge(clock)then
case state is
when a=>
if w=‘1’ then state<=b; else state<=a;end if;
when b=>
If w=’0’ then state<=a;
Else state<=b;
end if;
end case;
end process p0;
p1: process(state, input)
begin
case state is
when a=> if w=‘1’then z<=0;
end if;
when b=> if w=‘1’ then z<= 1
else z<=0;
end if;
end case;
end process p1;
end mealy_fsm;
 Meta-stability
• In General meta-stability is an un-avoidable behavior of the circuit that may cause
malfunction.
• From a specification point of view, synchronous elements such as flip flops specify a setup
time and hold time. (setup time: data should be stable for this time before arrival of clock)
(Hold time: data should be hold stable for this time after arrival of clock).
• Clock calculation depends upon setup time hold time and propagation delay
• If setup and hold time is violated then meta-stability will occur.
 WHAT IS METASTABILITY?
• Meta-stability in digital systems occurs
when two asynchronous signals combine in
such a way that their resulting output goes
to an indeterminate state. A common
example is the case of data violating the
setup and hold specifications of a latch or a
flip-flop. In an ideal world, where all logic
designs are synchronous and all inputs are
tied to the system clock, meta-stability
would not be a concern because all timing
conditions for the flip-flops would be met.
However, in most of the design, the data is
asynchronous w.r.t. the clock making the
flop a potential candidate for meta-stability
as there’s no reasonable way to insure that
the changing asynchronous data will meet
the flop’s setup time. Occasionally – not
often - the latched data will be corrupt. So
the designer has to take care of these
violations
 WHAT ARE THE CASES, WHEN METASTABILITY
OCCURS?

• As we have seen that whenever setup and hold violation time

occurs, meta-stability occurs, so it is to be seen when does this
signal violate this timing requirement.
• When the input signal is a asynchronous signal
• When the clock skew is more (rise time and fall time is
more then the tolerable values).
• When interfacing two domains operating at two different
frequency.
• When the combinational delay is such way that, it changes
flip-flop’s input in the required window (setup + hold
window)
 HOW TO MINIMIZE METASTABILITY?

• Synchronize any asynchronous input through one path that has at least one and
preferably two flip-flops in series. The flip-flops should be running on the same
edge of your system clock as the rest of the circuit.
• Design any state machines whose operation is affected by these “synchronized”
signals to follow a gray code pattern between states controlled by these signals.
Gray Code is a counting scheme where only a single bit changes between numbers
• Ensure that setup time of the destination flip-flop is met. This will avoid the
creation of metastable conditions inside the circuit and minimize the propagation
of any should they occur.
• Compute a parity or checksum of the input data before the capture register. Latch
that into the register as well. Have the code compute parity and compare it to that
read. If there's an error, do another read.
• Use metastability hardened Flip-flops.
 Noise margin
• Noise margin is a parameter closely related to the input-output voltage
characteristics. This parameter allows us to determine the allowable noise
voltage on the input of gate so that the output will not be affected.
• The specification most commonly used to specify noise margin in terms of
two parameters. LOW noise Margin NML and High noise Margin NMH
 Noise Margin

• Note that if either NML or NMH for gate are reduced below
0.1*Vdd, then the gate may be susceptible to switching noise
that may be present on the inputs. Apart from considering a
single gate , one must consider the net effect of noise sources
and noise margins on cascaded gates in assessing the overall
noise immunity of a particular system.

• Quite often noise margins are compromised to improve speed

of the circuit.
Noise Margin------
 Speed Performance

• Worst case rise delay= (Rp/n)*(m*n*Cd+Cr+kCg)

gate ,drain, routing capacitance, effective resistance of p device in
this gate, m-fan-in of gate,k-fanout,n width multiplier of p-device.

• Fall delay time = (Rn/n)*(m*n*r*Cg+q(k)*Cg+k*Cg))

• Rp=mRn

• BpWp=BnWn/m
• *q(k) function of routing capacitance
 Clock skew
• Clock skew is a phenomenon in synchronous circuits in
which the clock signal (sent from the clock circuit or
source or clock definition point) arrives at different
components at different times.
due to
• wire-interconnect length
• temperature variations
• capacitive coupling
• material imperfections and
• differences in input capacitance on the clock inputs
• these factor became more critical for high frequency
 Clock Skew--
• Negative skew
• positive skew
• Positive skew occurs when the transmitting register receives the
clock tick earlier than the receiving register.
Negative skew is occurs when the receiving register gets the clock
tick earlier than the sending reg
• Zero clock skew refers to the arrival of the clock tick simultaneously
at transmitting and receiving reg
• Useful Skew
clock skew can also benefit a circuit by decreasing the clock period
locally at which the circuit will operate correctly, it means skew add
more margin to meet setup. that is called useful skew
Positive Clock Skew:-Clock and data flow in the same
direction
Negative Clock Skew-Clock and data flow in opposite
directions
Clock Jitter- Deviation of clock edge from its ideal location in
time.
Misalignment of significant edges of a digital signal from their
ideal positions in time. Clock jitter is typically caused by clock
generator circuitry, noise, power supply variations,
interference from nearby circuitry etc.
 Clock distribution tree

• Need to reduce the skew on distributing the clock • This

requires us to reduce the wire delay, and the buffer delay -
But we can’t reduce the delay to the required levels (sub
100ps) so
• Make the effective delay small, by balancing the delays of all
the paths - Change a total delay problem to a matching problem
- Make ∆T much smaller than Tdrive Use a clock trees
• Match the delay on different branches of tree - If the buffer
delay matches - If the wire delay matches - Skew will be zero
• Obvious question: - How well can you match delays?
 Clock distribution
• Clock distribution tree.
• H-Tree.
• Balance tree network.
 D1
H Tree
D3
Buffer/delay element
D4

D2
• H tree provides equal delay to all terminals
• Widths are adjusted in such a way that the
skew throughout the H tree is equal.
• Buffers are added to amplify the degraded
clock( to increase driving capability).
• H tree can distribute a clock from the center
to within short distance on chip and maintains
an equal length.
 Clock Jitter
• Jitter is the timing variations of a set of signal
edges from their ideal values. Jitters in clock
signals are typically caused by noise or other
disturbances in the system. Contributing
factors include thermal noise, power supply
variations, loading conditions, device noise,
and interference coupled from nearby circuits.
 Types of Jitter
• Period Jitter
• Cycle to Cycle Period Jitter
• Long Term Jitter
• Phase Jitter
• Time Interval Error (TIE)
Supply and Ground Bounce
___________________________________
 It can be defined as variations in ground voltage due to impedance
on the ground wires
 Example : A and B are control inputs and turn on the NMOS
transistor at high logic (more than 0.7V).
 The output is high when Q2 turns off and Q1 turns on. Similarly, the
output is low when Q2 turns on and Q1 turns off. When the signal
transitions from high to low, Q2 provides a path for the current to
flow from the output to ground.

A typical Output Circuit

 There is some inductance in the very small lead wires between the chip
itself and the lead carrier of the package.

 This inductance is very small, but it is significant. Consider what happens

the moment Q2 turns on and Q1 turns off.

 A spike of current flows from the output through Q2 to ground. This current
flows through the inductance in the lead. The voltage across this inductance
(V Ref B) is directly related to the change in current as:

Effect of internal Inductance

Supply and Ground Bounce
___________________________________
 di/dt is related to the rise (and/or fall) time of the device. The faster
the rise and fall times, the smaller dt is, the greater di/dt (the change
in current per unit time) is, and the higher the voltage drop is across
any inductance.
 As Q2 turns on and the output voltage starts to fall, the voltage
between the output and Ref B falls just as before. The voltage at Ref
is relative to ground rises because of the current spike through the
lead inductance.
 Thus, V does not fall all the way, but "bounces" above ground
because of this inductive drop. This is the phenomenon called
ground bounce.
 Power distribution Techniques

• Power distribution presents several significant problems.

• First we must design a global power distribution network that
runs both VDD and Vss entirely in metal.
• We must size wire properly so that they can handle require
current.
• We must ensure that the transient behavior of the
distribution N/W does not cause a problem for logic to which
it supplies current.
• Tackle power supply loss (IR loss)
• Tackle power supply loss (I*di/dt loss).
 Power Distribution Techniques
___________________________________
Power network planarity
 Orient all the cells so that their
VDD pins are all on the same
side of a dividing line through the
cell, are guaranteed that a planar
routing exists.

Fig. A floor plan that isolates a ground pin

Metal Migration and Wire Sizing
 If too much current is carried through a
wire, the wire quickly disintegrates.
 Power lines are usually routed as
trees, with the power supply at the root
and the logic gates connected to the
Fig. Integrated power and ground trees twigs.
Power Distribution Techniques
___________________________________
Power distribution grids
 In a large chip, power is distributed using several metal
layers.
 The upper layers are larger in both width and height.
 The layers closer to the silicon are smaller in both
dimensions.
 Global power distribution happens on the upper layers;
connections on the lower layers move power down to the
circuits.

Power Distribution in BELLMAC 32A

Interconnect
Routing
Interconnect Routing Techniques
___________________________________
 Chip-level wiring design is usually divided into two phases:
 global routing assigns wires to routing channels between the
blocks.
 detailed routing designs the layouts for the wiring.
 Global Routing
 Routing Algorithms
 Utilization as metric
 Line Probe Routing

Fig. Line Probe Routing

Interconnect Routing Techniques
___________________________________
 Switchbox Routing
 A switchbox may be used to route wires between intersecting
channels.
 The track assignments at the ends of the channels define the
pins for the switchbox.
 It is often possible to define channels without requiring
switchboxes, but switchboxes may sometimes be necessary in
floor planning.

A switch Box formed at the

interconnection of two
channels
Power Optimization: Logic Gates
___________________________________
 Reduce Power consumption of isolated gate logic
 To make it change its output as few times as possible.
 Number of unnecessary changes to a gate’s output.
 The gate would not be useful if it never changed its
output value.
 To reduce the number of unnecessary changes to a
gate’s output
Glitches and Power
_______________________________________________

Glitching in a simple logic network

 Wire Parasitic
Wire Resistance
Rline = (*d)/(z*w)
•  -wire resistivity ,d- length of wire, z (t) – height of
interconnect conductor
• W- width
Wire Capacitance
(Side wall, bottom wall, Fringe, plate capacitance. )
Cline= C.d
C capacitance per unit length
d length
Wire Parasitic
___________________________________
 Wires, vias and transistors all introduce parasitic elements into our
circuits.
 Parasitic components are Resistance and capacitance
 Diffusion wire capacitance
 Bottom wall capacitance – depends on the diffusion area
 Side wall capacitance – depends on the perimeter

Sidewall and bottomwall

capacitances of a
diffusion region
 Wire Parasitic
___________________________________
 The depletion region capacitance value is given by
permittivity
of Si

depletion
capacitance depletion
at zero bias region width Built in
voltage

Junction capacitance decreases as

reverse voltage increases
Capacitive coupling between signals on
the same and different layers
___________________________________.
 Number of metal layers increases and the capacitance of
the substrate decrease.
 Wire to wire capacitance.
 Cm1m2 – capacitance between two different metal
layers, depends on are of overlap between two wires.
 Cw1w2 – two wires on same layer
 Signal Integrity Issues
• Reflection noise: Due to impedance mismatch,
stubs, vias and other discontinuity
• Cross talk: Due to electromagetic coupling
between signal and vias
• Power ground noise: Ground bounce and
power bounce
• Packaging: Packaging interconnect structure
Signal Integrity
___________________________________
 Signal can loose it’s integrity is when it becomes
distorted or when SNR begins to degrade.

 Signal distortion means that waveform of interest

begins to change shape.

 The degree to which this happen before it

becomes a problem depends very much on
application.
Signal Integrity Issues
___________________________________
 Rise Time and SI
 Transmission Lines,
 Reflection,
 Crosstalk
 Power/Ground Noise
Rise Time and SI
___________________________________
 The silicon size is shrinking dramatically and the
transistor channel length is greatly reduced into sub-
micron range.
 This trend leads to today’s logic families operating at
much higher speed.
 Their rise and fall time are on the order of hundreds of
picosecond.
 Many SI problems are directly related to dV/dt or dI/dt,
faster rise time significantly worsens some of the noise
phenomena such as ringing, crosstalk, and
power/ground switching noise.
Rise Time and SI
___________________________________
 Systems with faster clock frequency usually
have shorter rise time, therefore they will be
facing more SI challenges.
 A product is operating at 20Mhz clock frequency,
it may still get some SI problems that a 200MHz
system will have when modern logic families
with fast rise time are used.
Transmission Lines
___________________________________
 All the transmission lines have basic parameters such as
per-unit-length
 R (resistance),
 L (inductance),
 G (conductance) and
 C (capacitance), unit-length time delay (inverse of the
propagation speed), and characteristic impedance.
Reflection
___________________________________
 If the trace length is infinite, the wave/pulse will
never reflect and won’t distort the signal.

 Make it look like an infinite length by terminating

with high impedance equal to characteristics
impedance.

 Wires must be absolutely identical everywhere

along the length.
Reflection
___________________________________
 Reflections are not too bad problem if receiver is close
enough to sender.

 Track length is short.

 Reflection Coefficient: Value range between +1 to -1

 +1 is for open end
 -1 for short end
 0 means the trace is perfectly terminated.
Crosstalk
___________________________________
 Crosstalk, caused by EM
coupling between multiple
transmission lines running
parallel.

 The adjacent quiet signal lines

that may lead to false logic
switching.

 Crosstalk will also impact the

timing on the active lines if
multiple lines are switching
simultaneously.
 The amount of crosstalk is related to the

 signal rise time, to the spacing between the

lines, and
 to how long these multiple lines run parallel to
each other.

 Besides the crosstalk between traces, via

coupling is sometimes also important.
Guidelines for reducing the crosstalk
___________________________________
 Place traces in strip line environments.

 Minimize distance between trace and plane.

 Maximizes the separation between the traces

 Add ground guarding band in between the signal

lines
 One can make the lines space apart
 Signal Integrity Analysis

• System specification
• Architecture
• Interconnect characterization ,I/O Buffer, board and
connector
• Generate physical design guide lines, noise budget, Timing
Budget assessment.
• Component placement
• Constraint driven layout, final placement, critical routing
• Verification ,prototype, lab measurement.
• Meets Signal Integrality issues go ached.
I/O Architecture
___________________________________
 Pads and their associated drivers are distributed around the edge of
the chip.

 Advanced, high-density packaging schemes devote a layer of metal

to pads and distribute them across the entire chip face.

 Each pad must be large enough to have a wire (or a solder bump)
soldered to it.

 It must also include input or output circuitry, as appropriate.

I/O Block
Architecture of a pad frame
___________________________________
Pad Frame
___________________________________
 Each pad is built to a standard width and height, for
simplicity.
 Each pad has large VDD and VSS lines running through
it.
 A pad includes a large piece of metal to which the
external wire is soldered.
 If the pad requires external circuitry, it is usually put on
the side of the pad closest to the chip core.
 The chip core fits in the middle of the pad ring.
 If the pad ring is not completely filled with pads, spacers
are added to keep the power lines connected.
 The placement of pads around the ring is usually
determined by the required order of pins on the package.

 The wires to the package cannot be crossed without

danger of shorting, so if the package pins are required in
a certain order, the pads must be arranged in that order.

 The order of pins on the package determines routability
of the board and electrical noise among other things.

 The order of pins on a package has been known to

determine which candidate design wins a design contest.
 The pad is much larger than any single wire connected
to it, so the current in each direction is limited by the
outgoing wire.

 If we want to use multiple power pins to limit inductive

voltage drop, we can use several VDD and VSS pads
around the ring.

 VDD and VSS pads are the easiest pads to design

because they require no circuitry each is a blob of metal
connected to the appropriate ring.
Pad Design
___________________________________
 Pads and pad circuitry

 Pads used for input and output signals require

different supporting circuitry.

 A pad used for both input and output, sometimes

known by its trade name of Tri-state pin1,
combines elements of both inputs and output
pads.
Input pads
___________________________________
 The input pad may include circuitry to shift voltage levels
or otherwise condition the signal.

 The main job of an input pad is to protect the chip core

from static electricity.

 People or equipment can easily deliver a large static

voltage to a pin when handling a chip.

 MOS circuits are particularly sensitive to static discharge

because they use thin oxides.
 The gate oxide, which may be a few hundred Angstroms
thick, can be totally destroyed by a single static jolt,
shorting the transistor’s gate to its channel.

 An input pad puts protective circuitry between the pad

itself and the transistor gates in the chip core.

 Electrostatic discharge (ESD) can cause two types of

problems: dielectric rupture and charge injection.

 When the dielectric ruptures, chip structures can short

together.

 The charge injected by an ESD event can be sufficient to

damage the small on-chip devices.
Output pads
___________________________________
 Electrostatic discharge protection is not needed
for an output pad because the pad is not
connected to any transistor gate.
 The main job of an output pad is to drive the
large capacitances seen on the output pin.
 Within the chip, λ scaling ensures that we can
use smaller and smaller transistors, but the real
world doesn’t shrink along with our chip’s
channel length.
Output pads
___________________________________
A three-state pad circuit
___________________________________
 Three-state pads, used for both input and output.
 Pad can not, used as an input and output
simultaneously.
 Chip core is responsible for switching between modes.
 Pad requires electrostatic discharge protection for when
the pad is used as an input.
 An output driver for when it is used as an output, plus
circuitry to switch the pad between input and output
modes.

Input_mode=1
Thank you