Review Open Lab

The document presents a design for a low power-delay-product parallel signed multiplier using a radix-8 structure, which aims to enhance efficiency in digital signal processing and communication systems. By employing 3-bit grouping for partial product reduction and utilizing fast adders, the design demonstrates improved performance over traditional Booth multipliers. The methodology includes the use of tools like Vivado, Genus, and Tempus for simulation, synthesis, and timing analysis, respectively.

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Review Open Lab

Uploaded by

Vani telluri

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Available Formats

Download as PPTX, PDF, TXT or read online on Scribd

Simple low power-delay-product parallel signed

multiplier design using radix-8 structure with

efficient partial product reduction

21LIV604-Open Lab
Presented by
TELLURI VANI SAI [Link].P2VLD24024

Department of
Electronics and Communication Engineering
INTRODUCTION:

• Multipliers are widely used in DSP, processors, and communication systems but
take a lot of power, time, and chip area.

• Traditional Booth multipliers (radix-4) improve performance but are still not very
efficient for large designs.

• This project uses a radix-8 multiplier with 3-bit grouping to cut down the number
of partial products.

• The design applies fast adders and lightweight logic to reduce power use and
increase speed, giving better results than conventional multipliers.
09/15/2025
METHODOLOGY:

TOOLS USED:

• Vivado –> To simulate and verify RTL deign.

• Genus – > To generate gatelevel netlist and area, power reports.
• Tempus –> To generate timing reports.
FLOW:
TOOL EXPLORATION RESULTS: VIVADO

09/15/2025
RESULTS: GENUS

09/15/2025
RESULTS: TEMPUS

09/15/2025
TIME PLAN:
Month Work to be implemented Status

July 2025 Selection of project and tools to be explored

August 2025 Writing RTL to the architecture 1
September 2025 Synthesis of the architecture 1
October 2025 Writing RTL to the architecture 2
November 2025 Synthesis of the architecture 2

09/15/2025
REFERENCES:
• N. V. V. K. Boppana and S. Ren, “Simple low power–delay–product parallel signed multiplier design using
radix–8 structure with efficient partial product reduction,” The Journal of Engineering, vol. 2023, no. 7, p.
e12296, Jul. 2023, doi: 10.1049/tje2.12296.

• Waeijen, L., Jiao, H., Corporaal H., He Y.: Datawidth-aware energy-efficientmultipliers: a case for going sign
magnitude. In: Euromicro Conference on Digital System Design, pp. 54–61. IEEE, Piscataway, NJ (2018)

• Boppana, N.V.V.K., Kommareddy, J., Ren, S.: Low-cost and high_x0002_performance 8×8 Booth multiplier.
Circuits, Syst., Signal Process. 38(9),4357–4368 (2019). doi:[Link]

09/15/2025
THANK YOU

09/15/2025

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Review Open Lab

Uploaded by

Review Open Lab

Uploaded by

Simple low power-delay-product parallel signed

multiplier design using radix-8 structure with

• Vivado –> To simulate and verify RTL deign.

July 2025 Selection of project and tools to be explored

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