Michael De Nil

Another big milestone for Zero ASIC! Our Platypus family of open eFPGA just got a major upgrade in the relase of a set of heterogeneous eFPGAs with built in BRAM and DSP blocks. https://lnkd.in/e-HBARnG Platypus is the only eFPGA in the world guaranteeing: 100% open and standardized FPGA architectures 100% open source FPGA bitstream formats 100% open source FPGA development tools For the reasoning behind our open approach, check out the original Platypus announcement from earlier this year. https://lnkd.in/eyPxEUAX This awesome effort was led by Peter Grossmann, with tool chain contributions from Frederick Tombs, Wildebeest synthesis from Thierry Besson, and SiliconCompiler infrastructure from Peter Gadfort. With SoCs taking years to design and costing $100M - $1B to develop, I am always surprised more teams don't dedicate a portion of the silicon area to eFPGA logic. What's holding you back? Appreciate your thoughts and comments below.

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The cost-effective QFN package is popular in Analog ICs, but parasitics of the wirebonds can be a challenge in some applications. This is particularly true for RF ICs and DC/DC switching converters. For these applications, the FlipChip QFN package provides a logical solution. By bumping the die and flipping it onto the leadframe, FlipChip QFN combines the benefits of a standard QFN - affordability and standardization - with enhanced electrical performance and a smaller footprint. In automotive applications, FlipChip QFN also offers the option of plated-end leads, which aid in solder fillet formation, further enhancing reliability. Amkor QFN Homepage: https://bit.ly/4dAzAhS

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Unlocking 2nm Potential with Backside Power Delivery As TSMC hurtles toward 2026 mass production of its 2nm node, Backside Power Delivery (BSPDN) stands out as the game-changer. By moving power rails to the wafer’s backside, BSPDN slashes IR drop, frees up precious front-side routing, and paves the way for higher transistor densities, lower power consumption, and boosted performance. High Complexity, High Payoff Implementing BSPDN requires a series of technically demanding and tightly integrated processes, including: ▫️ Growing a SiGe etch-stop layer and a thin silicon cap layer for device fabrication. ▫️ Wafer bonding the device wafer to a carrier and then thinning the original wafer using CMP and etching down to the SiGe layer. ▫️ Performing Nano Through Silicon Vias (NTSV) by: - Passivating the wafer backside. - Etching nanoscale holes. - Depositing insulating layers via ALD. - Filling the vias with tungsten (W) for electrical connectivity. TSMC’s intricate BSPDN flow—spanning wafer bonding, ultra-precise thinning, and nanoscale through silicon vias that will not only drive chipmakers forward but also unleash new opportunities for equipment suppliers in bonding, CMP, etch/deposition, and inspection. Intel is rolling out its own backside PD (“PowerVia”) on the 18A node, and Samsung has slated similar technology for its 1.4nm equivalent process. The sub-2nm era is truly a power delivery battleground. Reference source: https://lnkd.in/gSrKPS9d Let’s shape the future together: 👉 https://lnkd.in/gJ3SSg8c #Semiconductors #2nm #BSPDN #TSV #TSMC #PowerVia #IntelFoundry #SamsungFoundry #AdvancedPackaging

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Lots of good coverage regarding Intel Foundry 18A node came during International Solid-State-Circuits Conference [ISSCC] 2025 conference last week. A very encouraging data point was that the SRAM density being achieved is similar to what TSMC is managing in its latest N2 node (which means it beats N3 by a good margin, SRAM is hard to shrink and density hasn't made that great a progress since N7) However Intel Corporation remains still plagued with yield issues it seems. https://lnkd.in/gKtm9HmF this report says yields are stuck at 30% range. Admittedly this is a lot better than 10% and usually once a process is at 30% it is a matter of time. Let's hope the foundry gets to 75% and higher by year end, if it does, this node will revive Intel and many people in the wider industry will rejoice

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Despite the rise of GPUs and custom ASICs, Saban emphasized that the core value of FPGAs remains: flexibility, time-to-market, and adaptability. 40 Years of FPGA: From Logic Cleanup to AI Acceleration https://lnkd.in/dbRh-cB3

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JEDEC Unveils HBM4 Standard: A Leap Forward for AI and HPC Performance JEDEC has officially released the High Bandwidth Memory 4 (HBM4) standard, marking a major advancement in memory technology tailored for AI, HPC, and advanced data center workloads. 🔹 Key Specs: – Bandwidth: Up to 2 TB/s, doubling HBM3E’s capability – Stack height: Up to 12-high DRAM stacks – Memory capacity: Up to 36 GB per stack – Supports both 2.5D and 3D (vertical interconnect) integration HBM4 separates the base die and logic die, allowing advanced packaging techniques like hybrid bonding. The standard also introduces a flexible memory subsystem interface to support diverse chiplet architectures—crucial for next-gen GPUs and AI accelerators. Why It Matters: With AI models requiring exponentially more memory bandwidth and capacity, HBM4 is expected to play a central role in sustaining compute performance scaling in a post-Moore’s Law era. JEDEC’s standard sets the foundation for upcoming product rollouts from major memory vendors and AI hardware developers. A major milestone for semiconductor design, memory architecture, and future-ready compute. Thanks again to DIGITIMES Asia for the full article with more background and insights click the source link in the comments below. #Semiconductors #HBM4 #JEDEC #AI #HPC #AdvancedPackaging #MemoryInnovation

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