RK3568平台支持CAN低速波特率

RK3568 CAN 波特率调试.

版本 日期 作者 内容 状态
1.0.0 2024-05-13 BePractiall 创建文档: 创建文件 未发布

查看时钟树

cat /d/clk/clk_summary

console:/ # cat /d/clk/clk_summary                                             
                                 enable  prepare  protect                                duty
   clock                          count    count    count        rate   accuracy phase  cycle
---------------------------------------------------------------------------------------------
 hym8563-clkout                       0        0        0       32768          0     0  50000
 rk808-clkout2                        0        0        0       32768          0     0  50000
 rk808-clkout1                        0        0        0       32768          0     0  50000
 clk_scmi_ddr                         0        0        0   324000000          0     0  50000
 clk_scmi_npu                         0        1        0   600000000          0     0  50000
 clk_scmi_gpu                         0        2        0   198000000          0     0  50000
 clk_scmi_cpu                         0        0        0  1992000000          0     0  50000
 xin32k                               0        0        0       32768          0     0  50000
 xin24m                              24       28        0    24000000          0     0  50000
    clk_cpu_boost                     0        0        0    24000000          0     0  50000
    clk_optc_arb                      1        1        0    24000000          0     0  50000
    clk_timer5                        0        0        0    24000000          0     0  50000
    clk_timer4                        0        0        0    24000000          0     0  50000
    clk_timer3                        0        0        0    24000000          0     0  50000
    clk_timer2                        0        0        0    24000000          0     0  50000
    clk_timer1                        0        0        0    24000000          0     0  50000
    clk_timer0                        1        1        0    24000000          0     0  50000
    dbclk_gpio                        0        0        0    24000000          0     0  50000
       dbclk_gpio4                    0        0        0    24000000          0     0  50000
       dbclk_gpio3                    0        0        0    24000000          0     0  50000
       dbclk_gpio2                    0        0        0    24000000          0     0  50000
       dbclk_gpio1                    0        0        0    24000000          0     0  50000
    clk_pwm3_capture                  0        0        0    24000000          0     0  50000
    clk_pwm3                          0        1        0    24000000          0     0  50000
    clk_pwm2_capture                  0        0        0    24000000          0     0  50000
    clk_pwm2                          0        1        0    24000000          0     0  50000
    ......

导出时钟树

adb shell cat d/clk/clk_summary > timeTree.txt

PS E:\CRT-9200-RK3568> adb shell cat d/clk/clk_summary > timeTree.txt
adb server version (40) doesn't match this client (41); killing...
* daemon started successfully

CAN时钟结构

                                 enable  prepare  protect                                duty
   clock                          count    count    count        rate   accuracy phase  cycle
---------------------------------------------------------------------------------------------
 xin24m                              24       28        0    24000000          0     0  50000
    pll_cpll                          1        1        0  1000000000          0     0  50000
       cpll                           4        5        0  1000000000          0     0  50000
          clk_can2                    0        0        0   200000000          0     0  50000
          clk_can1                    0        0        0   100000000          0     0  50000
          clk_can0                    0        0        0   100000000          0     0  50000
          aclk_vop_pre                1        2        0   500000000          0     0  50000
             aclk_vop                 1        3        0   500000000          0     0  50000
          clk_isp                     0        0        0   500000000          0     0  50000
          clk_gpu_src                 0        1        0   166666667          0     0  50000
             clk_gpu_pvtpll           0        0        0   166666667          0     0  50000
             clk_gpu_pvtm_core        0        0        0   166666667          0     0  50000
             clk_gpu_pre_mux          0        3        0   166666667          0     0  50000
                clk_gpu               0        2        0   166666667          0     0  50000
                pclk_gpu_pre          0        1        0    33333334          0     0  50000
                   pclk_gpu_pvtm       0        0        0    33333334          0     0  50000
                aclk_gpu_pre          0        1        0    83333334          0     0  50000

根据时钟树的结构, CAN模块的时钟源是来自于CPLL,CPLL是由xin24m锁相环进行倍频得到的。查看RK3568手册得知,CAN模块的时钟分频范围为1~32。
在这里插入图片描述

CAN波特率配置

查看CAN0的接口信息:ip -details link show can0

console:/ # ip link set can0 type can bitrate 500000
console:/ # ip -details link show can0
3: can0: <NOARP,ECHO> mtu 16 qdisc noop state DOWN mode DEFAULT group default qlen 10
    link/can  promiscuity 244976221 
    can state STOPPED (berr-counter tx 0 rx 0) restart-ms 0 
          bitrate 500000 sample-point 0.850 
          tq 100 prop-seg 8 phase-seg1 8 phase-seg2 3 sjw 1
          rockchip_can: tseg1 1..16 tseg2 1..8 sjw 1..4 brp 1..128 brp-inc 2
          clock 100000000numtxqueues 245000385 numrxqueues 244951991 gso_max_size 244996151 gso_max_segs 244957373 

根据CAN0的接口信息"rockchip_can: tseg1 1..16 tseg2 1..8 sjw 1..4 brp 1..128 brp-inc 2"可知,tseg1的范围为1~ 16,tseg2的范围为1~ 8,brp的范围为1~128且是偶数。根据RK3568手册得知,CAN波特率的计算公式为:rate = can_clk / (brp * (tseg1 + tseg2 + 1)),其中tseg1 = prop-seg+phase-seg1; tseg2 = phase-seg2; brp = can_clk*tq/10^9
在这里插入图片描述

配置波特率为10kbps

console:/ # ip link set can0 type can bitrate 10000                            
[R T N1E9T3L.I4N1K5 9a7n6s]w errockcshi:p _Mcaatnh  faer5g7u0m0e0n0t out of domain of func
.can can0: bitrate error 42949672.9% too high

当前CAN_CLK为100MHz,根据计算公式计算,能输出的波特率范围为31250~16666666,故当前的CAN_CLK时钟不支持输出1

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