Vivado DDR3仿真记录

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已于 2024-08-28 23:08:17 修改 · 1.9k 阅读

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#fpga开发

于 2024-06-05 21:23:23 首次发布

1、 init_calib_complete信号无法拉高

DDR3相关例程进行仿真时出现init_calib_complete一直未变成高电平，正常情况下，init_calib_complete一般在110us左右就会变为高电平，如果在仿真跑到200us后init_calib_complete仍未变成高电平，这种情况下可以将仿真停下来了不用继续仿真了。

解决方法：

1、打开Modelsim，等待初始化完毕，然后可以看到transcript会提示很多warning，然后我们可以锁定问题：

# WARNING: sim_tb_top.ddr3_top.u_mig_7series_0.u_mig_7series_0_mig.u_memc_ui_top_std.mem_intfc0.ddr_phy_top0.u_ddr_mc_phy_wrapper.u_ddr_mc_phy: The required delay though the phaser_in to internally match the aux_out clock  to ddr clock exceeds the maximum allowable delay. The clock edge  will occur at the output registers of aux_out 556.77 ps before the ddr clock  edge. If aux_out is used for memory inputs, this may violate setup or hold time.
# WARNING: Behavioral models for independent clock FIFO configurations do not model synchronization delays. The behavioral models are functionally correct, and will represent the behavior of the configured FIFO. See the FIFO Generator User Guide for more information.
# WARNING: Behavioral models for independent clock FIFO configurations do not model synchronization delays. The behavioral models are functionally correct, and will represent the behavior of the configured FIFO. See the FIFO Generator User Guide for more information.
# ** Error (suppressible): (vsim-8630) Infinity results from division operation.
#    Time: 0 fs  Iteration: 0  Process: /sim_tb_top/mem_rnk[0]/mem/gen_mem[0]/u_comp_ddr3/#ASSIGN#532 File: ../../../../imports/ddr3_model.sv Line: 532
# Warning : input CLKIN1 period and attribute CLKIN1_PERIOD on PLLE2_ADV instance sim_tb_top.ddr3_to