HDLBits-Dualedge

原创已于 2022-06-12 12:42:35 修改

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#Verilog

于 2022-06-10 11:17:28 首次发布

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该博客介绍了如何在FPGA中创建一个功能类似双沿触发触发器的电路。由于FPGA不支持双沿触发的触发器，作者通过组合两个单边沿触发的触发器来模拟双沿触发的行为。在给定的Verilog代码中，正边沿触发的DFF用于更新'n'寄存器，而负边沿触发的DFF则更新'p'寄存器。通过异或操作(p^n)，在每个时钟边缘，电路都能保持输入'd'的最新值，从而达到双沿触发的效果。

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You're familiar with flip-flops that are triggered on the positive edge of the clock, or negative edge of the clock. A dual-edge triggered flip-flop is triggered on both edges of the clock. However, FPGAs don't have dual-edge triggered flip-flops, and always @(posedge clk or negedge clk) is not accepted as a legal sensitivity list.你所熟悉的触发器是在时钟的正边或负边触发的。双边沿触发的触发器是在时钟的两个边沿上触发的。然而，FPGA没有双边沿触发的触发器，而且总是@(posedge clk或negedge clk)不被接受为合法的灵敏度列表。

Build a circuit that functionally behaves like a dual-edge triggered flip-flop:建立一个功能上类似于双沿触发触发器的电路。

官方答案：

module top_module(
	input clk,
	input d,
	output q);
	
	reg p, n;
	
	// A positive-edge triggered flip-flop
    always @(posedge clk)
        p <= d ^ n;
        
    // A negative-edge triggered flip-flop
    always @(negedge clk)
        n <= d ^ p;
    
    // Why does this work? 
    // After posedge clk, p changes to d^n. Thus q = (p^n) = (d^n^n) = d.
    // After negedge clk, n changes to d^p. Thus q = (p^n) = (p^d^p) = d.
    // At each (positive or negative) clock edge, p and n FFs alternately
    // load a value that will cancel out the other and cause the new value of d to remain.
    assign q = p ^ n;
    
    
	// Can't synthesize this.
	/*always @(posedge clk, negedge clk) begin
		q <= d;
	end*/
    
    
endmodule