【UVM】parameterized classes

1. SystemVerilog uses a “#” sign to list the Parameter names in a Class Header to define a Generic Class.
2. When we specify a default Parameter in a Class Header, we don’t have to provide an Overrides for that Parameter when referencing that Class.
3. A Generic Class & actual Parameter values is called a Specialization.
4. Static Class Properties do not get allocated unless their Class is Specialized. 
5. Every Specialization has unique set of Static Properties

以sequence為例(new_sequence override packet_sequence):

class packet_sequence #(CC_NUM = 3) extends uvm_sequence #(packet);

  int item_cnt = 10;