modelsim10.4仿真错误Error: (vlog-7) Failed to open design unit file "XXXXX" in read mode解决办法

Determining the location of the ModelSim executable... Using: E:\intelFPGA\18.1\modelsim_ase\win32aloem To specify a ModelSim executable directory, select: Tools -> Options -> EDA Tool Options Note: if both ModelSim-Altera and ModelSim executables are available, ModelSim-Altera will be used. **** Generating the ModelSim Testbench **** quartus_eda --gen_testbench --tool=modelsim_oem --format=verilog --write_settings_files=off 1 -c 1 --vector_source="E:/intelFPGA/WORK/Waveform.vwf" --testbench_file="E:/intelFPGA/WORK/simulation/qsim/Waveform.vwf.vt" Info: ******************************************************************* Info: Running Quartus Prime EDA Netlist Writer Info: Version 18.1.0 Build 625 09/12/2018 SJ Standard Edition Info: Copyright (C) 2018 Intel Corporation. All rights reserved. Info: Your use of Intel Corporation's design tools, logic functions Info: and other software and tools, and its AMPP partner logic Info: functions, and any output files from any of the foregoing Info: (including device programming or simulation files), and any Info: associated documentation or information are expressly subject Info: to the terms and conditions of the Intel Program License Info: Subscription Agreement, the Intel Quartus Prime License Agreement, Info: the Intel FPGA IP License Agreement, or other applicable license Info: agreement, including, without limitation, that your use is for Info: the sole purpose of programming logic devices manufactured by Info: Intel and sold by Intel or its authorized distributors. Please Info: refer to the applicable agreement for further details. Info: Processing started: Thu May 22 00:35:13 2025 Info: Command: quartus_eda --gen_testbench --tool=modelsim_oem --format=verilog --write_settings_files=off 1 -c 1 --vector_source=E:/intelFPGA/WORK/Waveform.vwf --testbench_file=E:/intelFPGA/WORK/simulation/qsim/Waveform.vwf.vt Warning (18236): Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance. Completed successfully. Completed successfully. **** Generating the functional simulation netlist **** quartus_eda --write_settings_files=off --simulation --functional=on --flatten_buses=off --tool=modelsim_oem --format=verilog --output_directory="E:/intelFPGA/WORK/simulation/qsim/" 1 -c 1 Info: ******************************************************************* Info: Running Quartus Prime EDA Netlist Writer Info: Version 18.1.0 Build 625 09/12/2018 SJ Standard Edition Info: Copyright (C) 2018 Intel Corporation. All rights reserved. Info: Your use of Intel Corporation's design tools, logic functions Info: and other software and tools, and its AMPP partner logic Info: functions, and any output files from any of the foregoing Info: (including device programming or simulation files), and any Info: associated documentation or information are expressly subject Info: to the terms and conditions of the Intel Program License Info: Subscription Agreement, the Intel Quartus Prime License Agreement, Info: the Intel FPGA IP License Agreement, or other applicable license Info: agreement, including, without limitation, that your use is for Info: the sole purpose of programming logic devices manufactured by Info: Intel and sold by Intel or its authorized distributors. Please Info: refer to the applicable agreement for further details. Info: Processing started: Thu May 22 00:35:14 2025 Info: Command: quartus_eda --write_settings_files=off --simulation=on --functional=on --flatten_buses=off --tool=modelsim_oem --format=verilog --output_directory=E:/intelFPGA/WORK/simulation/qsim/ 1 -c 1 Warning (18236): Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance. Info (204019): Generated file 1.vo in folder "E:/intelFPGA/WORK/simulation/qsim//" for EDA simulation tool Info: Quartus Prime EDA Netlist Writer was successful. 0 errors, 1 warning Info: Peak virtual memory: 4725 megabytes Info: Processing ended: Thu May 22 00:35:15 2025 Info: Elapsed time: 00:00:01 Info: Total CPU time (on all processors): 00:00:01 Completed successfully. **** Generating the ModelSim .do script **** E:/intelFPGA/WORK/simulation/qsim/1.do generated. Completed successfully. **** Running the ModelSim simulation **** E:/intelFPGA/18.1/modelsim_ase/win32aloem/vsim -c -do 1.do Reading E:/intelFPGA/18.1/modelsim_ase/tcl/vsim/pref.tcl # 10.5b # do 1.do # ** Warning: (vlib-34) Library already exists at "work". # couldn't execute "E:\intelFPGA\18.1\modelsim_ase\win32aloem\vlog": invalid argument # couldn't execute "E:\intelFPGA\18.1\modelsim_ase\win32aloem\vlog": invalid argument # vsim -novopt -c -t 1ps -L cyclonev_ver -L altera_ver -L altera_mf_ver -L 220model_ver -L sgate_ver -L altera_lnsim_ver work.1_vlg_vec_tst # Start time: 00:35:15 on May 22,2025 # ** Error: (vsim-3170) Could not find 'work.1_vlg_vec_tst'. # Searched libraries: # E:/intelFPGA/18.1/modelsim_ase/altera/verilog/cyclonev # E:/intelFPGA/18.1/modelsim_ase/altera/verilog/altera # E:/intelFPGA/18.1/modelsim_ase/altera/verilog/altera_mf # E:/intelFPGA/18.1/modelsim_ase/altera/verilog/220model # E:/intelFPGA/18.1/modelsim_ase/altera/verilog/sgate # E:/intelFPGA/18.1/modelsim_ase/altera/verilog/altera_lnsim # E:/intelFPGA/WORK/simulation/qsim/work # Error loading design Error loading design # End time: 00:35:16 on May 22,2025, Elapsed time: 0:00:01 # Errors: 1, Warnings: 0 Error.