ARM cores

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分类专栏： Arm指令集架构文章标签： cache extension performance branch up io

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ARM cores

ARM provides a summary of the numerous vendors who implement ARM cores in their design.^{[ 11]} KEIL also provides a somewhat newer summary of vendors of ARM based processors.^{[ 12]} ARM further provides a chart^{[ 13]} displaying an overview of the ARM processor lineup with performance and functionality versus capabilities for the more recent ARM7, ARM9, ARM11, Cortex-M, Cortex-R and Cortex-A device families.

ARM Family	ARM Architecture	ARM Core	Feature	Cache (I/D), MMU	Typical MIPS @ MHz
ARM1	ARMv1	ARM1	First implementation	None
ARM2	ARMv2	ARM2	ARMv2 added the MUL (multiply) instruction	None	4 MIPS @ 8 MHz 0.33 DMIPS /MHz
ARM2	ARMv2a	ARM250	Integrated MEMC (MMU), Graphics and IO processor. ARMv2a added the SWP and SWPB (swap) instructions.	None, MEMC1a	7 MIPS @ 12 MHz
ARM3	ARMv2a	ARM3	First integrated memory cache.	4 KB unified	12 MIPS @ 25 MHz 0.50 DMIPS/MHz
ARM6	ARMv3	ARM60	ARMv3 first to support 32-bit memory address space (previously 26-bit)	None	10 MIPS @ 12 MHz
		ARM600	As ARM60, cache and coprocessor bus (for FPA10 floating-point unit).	4 KB unified	28 MIPS @ 33 MHz
		ARM610	As ARM60, cache, no coprocessor bus.	4 KB unified	17 MIPS @ 20 MHz 0.65 DMIPS/MHz
ARM7	ARMv3	ARM700		8 KB unified	40 MHz
		ARM710	As ARM700, no coprocessor bus.	8 KB unified	40 MHz
		ARM710a	As ARM710	8 KB unified	40 MHz 0.68 DMIPS/MHz
ARM7TDMI	ARMv4T	ARM7TDMI(-S)	3-stage pipeline, Thumb	none	15 MIPS @ 16.8 MHz 63 DMIPS @ 70 MHz
		ARM710T	As ARM7TDMI, cache	8 KB unified, MMU	36 MIPS @ 40 MHz
		ARM720T	As ARM7TDMI, cache	8 KB unified, MMU with Fast Context Switch Extension	60 MIPS @ 59.8 MHz
		ARM740T	As ARM7TDMI, cache	MPU
ARM7EJ	ARMv5TEJ	ARM7EJ-S	5-stage pipeline, Thumb, Jazelle DBX, Enhanced DSP instructions	none
ARM8	ARMv4	ARM810^{[ 14]}	5-stage pipeline, static branch prediction, double-bandwidth memory	8 KB unified, MMU	84 MIPS @ 72 MHz 1.16 DMIPS/MHz
StrongARM	ARMv4	SA-1	5-stage pipeline	16 KB/8–16 KB, MMU	203–206 MHz 1.0 DMIPS/MHz
ARM9 TDMI	ARMv4T	ARM9TDMI	5-stage pipeline, Thumb	none
		ARM920T	As ARM9TDMI, cache	16 KB/16 KB, MMU with FCSE (Fast Context Switch Extension)^{[ 15]}	200 MIPS @ 180 MHz
		ARM922T	As ARM9TDMI, caches	8 KB/8 KB, MMU
		ARM940T	As ARM9TDMI, caches	4 KB/4 KB, MPU
ARM9E	ARMv5TE	ARM946E-S	Thumb, Enhanced DSP instructions, caches	variable, tightly coupled memories, MPU
		ARM966E-S	Thumb, Enhanced DSP instructions	no cache, TCMs
		ARM968E-S	As ARM966E-S	no cache, TCMs
	ARMv5TEJ	ARM926EJ-S	Thumb, Jazelle DBX, Enhanced DSP instructions	variable, TCMs, MMU	220 MIPS @ 200 MHz,
	ARMv5TE	ARM996HS	Clockless processor, as ARM966E-S	no caches, TCMs, MPU
ARM10E	ARMv5TE	ARM1020E	6-stage pipeline, Thumb, Enhanced DSP instructions, (VFP)	32 KB/32 KB, MMU
	ARMv5TE	ARM1022E	As ARM1020E	16 KB/16 KB, MMU
	ARMv5TEJ	ARM1026EJ-S	Thumb, Jazelle DBX, Enhanced DSP instructions, (VFP)	variable, MMU or MPU
XScale	ARMv5TE	XScale	7-stage pipeline, Thumb, Enhanced DSP instructions	32 KB/32 KB, MMU	133–400 MHz
		Bulverde	Wireless MMX , Wireless SpeedStep added	32 KB/32 KB, MMU	312–624 MHz
		Monahans ^{[ 16]}	Wireless MMX2 added	32 KB/32 KB (L1), optional L2 cache up to 512 KB, MMU	up to 1.25 GHz
ARM11	ARMv6	ARM1136J(F)-S^{[ 17]}	8-stage pipeline, SIMD , Thumb, Jazelle DBX, (VFP), Enhanced DSP instructions	variable, MMU	740 @ 532–665 MHz (i.MX31 SoC), 400–528 MHz
	ARMv6T2	ARM1156T2(F)-S	9-stage pipeline, SIMD , Thumb-2, (VFP), Enhanced DSP instructions	variable, MPU
	ARMv6ZK	ARM1176JZ(F)-S	As ARM1136EJ(F)-S	variable, MMU + TrustZone	965 DMIPS @ 772 MHz, up to 2 600 DMIPS with four processors^{[ 18]}
	ARMv6K	ARM11 MPCore	As ARM1136EJ(F)-S, 1–4 core SMP	variable, MMU
Cortex-A	ARMv7-A	Cortex-A5^{[ 19]}	VFP, NEON, Jazelle RCT, Thumb/Thumb-2, 1–4 cores	variable (L1 + L2), MMU + TrustZone	1.57 DMIPS / MHz per core
		Cortex-A8	VFP, NEON, Jazelle RCT, Thumb-2, 13-stage superscalar pipeline	variable (L1 + L2), MMU + TrustZone	up to 2 000 (2.0 DMIPS/MHz in speed from 600 MHz to greater than 1 GHz)
		Cortex-A9 MPCore	Application profile, VFPv3 FPU, NEON, Thumb-2, Jazelle RCT/DBX, out-of-order speculative issue superscalar , 1–4 core SMP	32 KB/32 KB L1, up to 4 MB L2, MMU + TrustZone	2.5 DMIPS/MHz per core, 10 000 DMIPS @ 2 GHz on Performance Optimized TSMC 40G (dual core)
		Cortex-A15 MPCore	Application profile, VFPv4 FPU, NEON, Thumb-2, Jazelle RCT/DBX, out-of-order speculative issue superscalar, Large Physical Address Extensions (LPAE), Hardware virtualization, 1–4 SMP cores	32 KB/32 KB L1, up to 4 MB L2, MMU + TrustZone
Cortex-R	ARMv7-R	Cortex-R4(F)	Real-time profile, Thumb-2, (FPU)	variable cache, MPU optional	600 DMIPS @ 475 MHz
Cortex-M	ARMv6-M	Cortex-M0	Microcontroller profile, Thumb-2 subset (16-bit Thumb instructions & BL, MRS, MSR, ISB, DSB, and DMB). Hardware multiply instruction optional	No cache.	0.9 DMIPS/MHz
	ARMv6-M	Cortex-M1	FPGA targeted, Microcontroller profile, Thumb-2 subset (16-bit Thumb instructions & BL, MRS, MSR, ISB, DSB, and DMB).	None, tightly coupled memory optional.	Up to 136 DMIPS @ 170 MHz^{[ 20]} (0.8 DMIPS/MHz,^{[ 21]}  MHz achievable FPGA-dependent)
	ARMv7-M	Cortex-M3	Microcontroller profile, Thumb-2 only. Hardware divide instruction.	no cache, MPU optional.	125 DMIPS @ 100 MHz
	ARMv7-ME	Cortex-M4	Microcontroller profile, both Thumb and Thumb-2, FPU. Hardware MAC, SIMD and divide instructions.	MPU optional.	1.25 DMIPS/MHz
ARM Family	ARM Architecture	ARM Core	Feature	Cache (I/D), MMU	Typical MIPS @ MHz