小柴带你学AutoSar系列一、基础知识篇（6）车规级MCU入门RH850

CPU0/1/2/3 core
- RH850G4MH2
CPU0/1/2/3 instruction cache memory (for Code Flash)
- 16 KB
CPU0/1/2/3 data buffer (for Code Flash)
- 4 lines (256 bit/line)
Minimum CPU0/1/2/3 instruction execution time
- 2.5ns (during internal 400 MHz operation)
General CPU0/1/2/3 registers
- Thirty-two 32-bit registers
CPU0/1/2/3 instruction sets
- Signed multiplication (32 bits × 32 bits → 64 bits): 1 to 2 CPU clocks
- Saturated operation instructions (with overflow/underflow detection function)
- 32-bit arithmetic/logical shift instructions: 1 CPU clock
- Bit manipulation instructions
- Load/store instructions with long/short formats
- Signed load instructions
Inter-Processor Interrupt (IPIR)
- Support of inter-Processor interrupt function of 4 channels
- Support level detection of interrupts
- Accessible from all clusters and all PEs
- identification of interrupt request source PE is possible.
- Unintended inter-PE interrupts can be prevented by masking interrupt requests.
- SET1, CLR1, and NOT1 can be executed as atomic operation instructions to IPIR.
Barrier-Synchronization (BARR)
- The 16-ch barrier synchronization registers are provided. Barrier synchronization can be implemented using the same code for all the cores. Accessible from all clusters and all PEs within the systemTime Protection Timer (TPTM) Interval timer × 2ch (down counter), free-run timer × 1ch (up counter), up timer × 2ch (up counter)Start, Stop and Restart of counter for the interval timers, the free-run timer and the up timers.
- Divided counter of the timers can be configured for the interval timers, the free-run timer, up timer respectively.
- Simultaneous count control for the interval timers belonging to the same PE.
- Simultaneous count control for the up timers belonging to the same PE using registers prepared for each PE.
- Globally simultaneous count control registers are prepared. A PE can control all up counters including ones owned by other PEs.
- Underflow interrupt for the interval timers.
- Comparison value matching interrupts for the up timers.
- Each timer set has 3 control signals to stop timers while in debug mode. One is for interval timers and the free-run timer, another is for up timer 0, the other is for up timer 1.
Memory space
- 4-GB address space (common to program and data)
Code flash
- 16 MB (common to each CPU, ICUMHA) [For U2A-EVA and U2A16 Only]
- User area: 8 MB (common to each CPU, ICUMHA) [For U2A8 Only]
- User area: 6 MB (common to each CPU, ICUMHA) [For U2A6 Only]
- User boot area: 64 KB high-speed reading through cache enabled.
- Two types of memory area– User area:
- OTA (Over-the-Air) update support
Data flash
- 512 KB + 64 KB (dedicated to ICUMHA) [For U2A-EVA and U2A16 Only]
- 256 KB + 64 KB (dedicated to ICUMHA) [For U2A8 Only]
- 192 KB + 64 KB (dedicated to ICUMHA) [For U2A6 Only]
RAM
- Local RAM: 64 KB (CPU0/1/2/3 [For U2A-EVA and U2A16 Only])
- Local RAM: 64 KB (CPU0/1 [For U2A8 and U2A6 Only])
- Cluster RAM: 3328 KB (common to each CPU) (256 KB: Retention RAM) [For U2A-EVA and U2A16 Only]
- Cluster RAM: 1664 KB (common to each CPU) (128 KB: Retention RAM) [For U2A8 Only]
- Cluster RAM: 640 KB (common to each CPU) (128 KB: Retention RAM) [For U2A6 Only]
- Cluster Emulation RAM: 2 MB (1 MB for each cluster 0 & 1) [For U2A-EVA Only]
- Cluster Emulation RAM: 32 KB (cluster 0) [For U2A6 Only]
- Global Emulation RAM: 2 MB [For U2A-EVA Only]
Serial Flash Memory I/F (SFMA)
- 1 unit incorporated [For U2A-EVA, U2A16, U2A8, U2A6 (BGA-292) and U2A6 (QFP-176) Only]One serial Flash Memory device can be connected.
- A data bus width of 1 bit, 2 bits, or 4 bits can be selected.
- 4 GB address space
- Efficient data reception due to built-in read cache (64-bit line × 16 entries)
- Arbitrary bit rate settable by the on-chip baud rate generator
Multimedia Card Interface (eMMC)
- 1 unit incorporated [For U2A-EVA, U2A16, U2A8, U2A6 (BGA-292) and U2A6 (QFP-176) Only]
- Compliant with JEDEC STANDARD JESD84-A441 (neither DDR mode nor 1.8-V operation is supported).
- Supports 1-/4-/8-bit MMC bus widths.
- Supports the backward-compatible mode.
- High-speed mode is supported.
- MMC Clock frequency = MMCA module clock frequency/2k (k = 1 to 10).
- Supports block transfer.
- Supports boot operation.
- Supports high priority interrupts (HPI).
- Supports background operation.
- Interrupt requests: normal operation and error/timeout.
- DMA transfer requests: buffer write and buffer read.
Interrupts/exceptions
- 1 non-maskable interrupt (NMI pin)
- 1 FE level interrupt
- 768 maskable interrupts (high-speed: 32, low-speed: 736)
- Simultaneous distribution of interrupt sources to multiple cores (each CPU)
- Applicable sources: non-maskable interrupt (NMI pin), FE level interrupt, 32 high-speed maskable interrupts
- External interrupt input function (IRQ pins)
- Software interrupt function (SINT)
- Inter-processor interrupt function (IPIR)
- 64-level priority specifiable for maskable interrupts
- For RH850G4MH2 exceptions, see Section 3.2.4, Exceptions and Interrupts.
sDMA controller
- 32 channels incorporated (16 channels × 2 units)
- Transfer data length: 1 byte, 2 bytes, 4 bytes, 8 bytes, 16 bytes, 32 bytes, 64 bytes
- Parallel reads and writes (fly-by)
- Address mode: dual address mode
- Transfer requests: auto request, peripheral hardware request.
- Bus modes: normal speed mode, slow speed mode
- Arbitration modes: fixed priority mode, round-robin modeInterrupt requests: termination of descriptor step, the termination of data transfer, the occurrence of address error.
- Descriptor memory: 8 KB (shared at all channels).
- Scatter-gather transfer
- Transfer target: On-chip memory, on-chip peripheral modules (excluding DTS and sDMAC)
DTS controller
- 128 channels incorporated
- Transfer unit: 8 bits/16 bits/32 bits/64 bits/128 bits64-bit × 2-burst transfer
- Dual-address transfer mode
- Address reloading function
- Chain transfer function
- Three transfer modes: Single transfer, block transfer 1 (specified by number of transfer times), and block transfer 2 (specified by address count)
- Transfer target: On-chip memory, on-chip peripheral modules (excluding the DTS and sDMAC)
- Transfer requests can be set by interrupt sources and the software.
I/O
- Output driving ability of specific input/output pins is selectable
- Inversion or non-inversion of output values of specific input/output pins is selectable
- Pull-up or pull-down off of specific input/output pins is selectable
Safety functions
- Flash memory ECC error detection function
- RAM ECC error detection function
- Peripheral module RAM ECC error detection function (e.g. FlexRay, CAN, GTM)
- Clock monitor
- Error Control Module (ECM)
- Duplexing of modules (e.g. CPUs, ECM, error output pins)
- Automatic Power-on BIST execution after reset
- Standby Resume BIST (SR-BIST) execution selection after wake-up from DeepSTOP mode.
Error Control Module (ECM)
- Collects information for each error check system and safety function and indicates error status.
- When an error is detected, an error signal can be output from the error pin to the external.
- Interrupts and internal reset signals can be generated upon detection of an error.
- Provided with a function to generate a pseudo-error for debugging and self-diagnosis.
Data CRC Function (KCRC)
- The data CRC (Cyclic Redundancy Check) function can verify or generate data streams protected by a CRC with various lengths and different bit widths.
Window Watchdog Timer (WDTB)
- 5 units incorporated [For U2A-EVA and U2A16 Only]
- 3 units incorporated [For U2A8 and U2A6 Only]
- Can generate a signal to the ECM when a counter overflows (timer expires).
- Can generate an interrupt at 75% of the counter overflow value.
- An interrupt request can be generated at any function of the counter value.
- A window open period can be set to any function of the counter value.
Long-Term System Counter (LTSC)
- 1 unit incorporated
- 64-bit counter without overflow.
- Free-run up counting
- Atomic read/write access to all registers
- Anytime read access to counter registers
- Application reset (SW reset) can be masked. When masked, counter keeps running on reset occurrence and counter register will not be initialized.
OS Timer (OSTM)
- 10 units incorporated [For U2A-EVA and U2A16 Only]
- 8 units incorporated [For U2A8 and U2A6 Only]
- A 32-bit timer assuming use by OS
- Interval timer mode or free-running timer mode selectable
- Synchronous start between units available
Timer Array Unit D (TAUD)
- 16 channels, 16-bit counter and 16-bit data register per channel
- Independent channel operation
- Synchronous channel operation (master and slave operation)
- Generation of different types of output signal
- Real-time output
- Counter can be triggered by external signal
- Interrupt generation
- The TAUD can operate independently or synchronously (combine with other channels)
- 3 units incorporated
- The TAUD has the following functions:
Timer Array Unit J (TAUJ)
- Independent channel operation function (operated using a single channel)
- Synchronous channel operation function (operated using a master channel and multiple slave channels)
- 4 units incorporated
- The TAUJ has the following functions:
- The TAUJ can operate independently or synchronously (combine with other channels)
Motor Control Timer (TSG3)
- Simultaneous active output detect function for positive and inverse phase.
- Abnormal input detection function of the three-phase encoder
- 2 units incorporated [For U2A-EVA, U2A16, U2A8, U2A6 (BGA-292) and U2A6 (QFP-176) Only]
- 1 unit incorporated [For U2A6 (BGA-156) and U2A6 (QFP-144) Only]
- 18-bit timer counter
- Count clock resolution: Minimum 12.5 ns (count clock = 80 MHz)
- Operating mode corresponding to various motor control methods
- Compare registers with reload buffer
- 10-bit dead time counter
- A/D conversion trigger signal generation
- Forced output stop function by TAPA
- Reload (simultaneous rewrite) or anytime rewrite
- HT-PWM mode with 0-100% duty cycles output
- Semi-automatic cruise function
- Three-phase encoder function (hall sensor signals can be input).
- Fail-safe function (warning interrupt or error interrupt can be generated)
Timer Option (TAPA)
- Asynchronous Hi-Z control function
- Interrupt signal output function
- A/D conversion start trigger selection function
- 4 units incorporated [For U2A-EVA, U2A16, U2A8 and U2A6 (BGA-292) Only]
- 3 units incorporated [For U2A6 (QFP-176) Only]
- 2 units incorporated [For U2A6 (BGA-156) and U2A6 (QFP-144) Only]
- Combine with the peripheral interconnect (PIC) to provide the following functions:
Timer Pattern Buffer (TPBA)
- Period-matched detection interrupt
- Duty-cycle-matched detection interrupt
- Number-of-patterns matched detection interrupt
- 2 units incorporated
- Count clock resolution: Minimum 12.5 ns (count clock = 80 MHz)
- 16-bit counte
- 16-bit duty register
- 16-bit period setting register
- 7-bit address counter register
- 7-bit pattern number setting register
- Interrupt request signals
  
  Number of duty patterns– 64 patterns (16 bits) or 128 patterns (8 bits)
- Automatic duty generation according to the number of patterns
- Output control by software
- The count clock can be selected from PCLK, PCLK/2, PCLK/4, and PCLK/8 according to the prescaler set value.
- Synchronous start with another timer
PWM Output/Diagnostic (PWM-Diag)
- 1 PWBA block for generating clock signals.
- Generates a count clock signal for PWGC
- 96 PWGC blocks generate PWM signals. [For U2A-EVA, U2A16, U2A8 and U2A6 (BGA-292) Only]
- 76 PWGC blocks generate PWM signals. [For U2A6 (QFP-176) Only]
- 50 PWGC blocks generate PWM signals. [For U2A6 (BGA-156) Only]
- 64 PWGC blocks generate PWM signals. [For U2A6 (QFP-144) Only]
- Outputs PWM waveforms and A/D conversion trigger to PWSD
- 1 PWSD block for generating triggers for A/D conversion.
- Transmits the required setting information to the A/D converter and outputs the A/D conversion start trigger
Real-Time Clock (RTCA)
- 1 unit incorporated
- Count clock selection from 240 kHz to 2.5 MHz
- Counters for years, months, day of the month, day of the week, hours, minutes, seconds, and a subcounter.
- One Hz pulse output function
- Fixed interval interrupt function
- Alarm interrupt function
Peripheral Interconnect function (PIC1)
- 1 unit incorporated
- Simultaneous start trigger function
- INT signal output selection function
- PWM/Delay pulse output function with dead time
- Trigger pulse width measurement function
- Encoder capture trigger select function
- Two-phase encoder control function
- Three-phase pulse input control function
- Three-phase encoder control function
- TAUD input select function
- Hi-Z control function
- Timer output monitor function (PWM-Diag)
- Timer input monitor function
- TSG3 Synchronous Clear Function
Peripheral Interconnect function (PIC2)
- Baud Rate Measurement for an UART (RLIN3)
- Hi-Z Control Function Over External Pin for GTM Output
- GTM Output Monitor for PWM Diagnostic
- ENCA Trigger Selection Function
- PSI5S Timestamp and the Sync Pulse Signal Selection Function
- GTM Timer Input (TIM) Selection Function
- ENCA Encoder Input Selection
- 3 units incorporated
- ADCJ trigger select function
- Signal routing function for GTM: