HDLbits题解之--5.Verification:Writing testbenchs

本文链接：https://blog.csdn.net/qq_33155311/article/details/126563051

本文通过几个具体的Verilog代码示例介绍了时序逻辑和组合逻辑的设计方法。包括了基本的时钟生成模块、测试平台搭建、逻辑门级设计及触发器实现等内容。这些示例有助于理解如何在FPGA设计中运用Verilog进行硬件描述。

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Clock

`timescale 1ps/1ps
module top_module ( );
	reg clk;
    real	CYCLE = 10;
    always begin
        clk = 0;#(CYCLE/2) ;       
        clk = 1;#(CYCLE/2);
    end        
        dut u_dut(
            .clk(clk)
		);
endmodul

Testbench1

module top_module ( output reg A, output reg B );//
    // generate input patterns here
    initial begin
		A = 1'b0;
        #10 A=1'b1;
        #10	A=1'b0;
    end
    
	initial begin
       B=1'b0;
       #15 B=1'b1;
       #25 B=1'b0;
    end
endmodule

AND gate

module top_module();
    reg [1:0] in;
    wire	out;
    initial begin
        in[0] = 'b0;
        #10 in[0] = 1'b1;
        #10 in[0] = 1'b0;
        #10 in[0] = 1'b1;
    end
    initial begin
        in[1] = 1'b0;
        #20 in[1] = 1'b1;
    end
    
    andgate u_andgate(
        .in(in),
        .out(out)  
    );
endmodule

Testbench2

module top_module();
	reg clk;
    reg in;
    reg [2:0] s;
    wire out;

    real CYCLE = 10;
    always begin
        clk=0;#(CYCLE/2); 
        clk=1;#(CYCLE/2); 
    end
    initial begin
       in = 1'b0;
        #20 in = 1'b1;
        #10 in = 1'b0;
        #10 in = 1'b1;
        #30 in = 1'b0;
    end
    
    initial begin
       s=2;
        #10 s=6;
        #10 s=2;
        #10 s=7;
        #10 s=0;
    end
    
    q7 u_q7(
        .clk(clk),
        .in(in),
        .s(s),
        .out(out)   
    );
endmodule

T flip-flop

module top_module ();
	reg clk;
    reg reset;   
    reg t;      
    wire q;    
    real CYCLE = 10;
    always begin
        clk = 0;#(CYCLE/2);
        clk = 1;#(CYCLE/2);
    end
    initial begin
        reset = 1;
        t=0;
        
        #10
        reset =0;
        t=1;
    end
    tff u_tff(
        .clk(clk),
        .reset(reset),
        .t(t),
        .q(q)
    );
endmodule