后端设计笔记 08 DFM

集美战队蔡旭

已于 2025-05-28 20:40:20 修改

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文章标签：笔记

于 2025-05-27 21:56:22 首次发布

本文链接：https://blog.csdn.net/qq_39585560/article/details/148241329

1.理论

下面的可以在congestion较多的情况下使用

做STA先用STARRC进行抽取spef ，还要读入netlist.v，如果不改规则，那么spef和.v里面net名字不一致，该命令会将设计中不符合Verilog语法规范的命名（如包含冒号、空格等特殊字符）自动转换为合法格式。例如，将层次分隔符:替换为_，避免后续仿真工具因非法字符报错

先保存CEL，删除一些单元后再输出做lvs的.v文件，随后复原备份设计 → 移除干扰单元 → 导出完整网表 → 恢复原始数据

pt用的.v不能包含dcap和filler

lvs用的不能包含filler，一般std库里的.sdl没有filler，必须包含dcap，因为dcap是器件与网络有链接

2.实践

怎样消除少量的DRC

绕线完成后发现短路，先删除所有布线

remove_net_shape [get_net_shapes -filter "net_type==Clock"]
remove_via [get_vias -filter "net_type==Clock"]

再做修改

1，route_zrt_detail -incremental true ；命令自动修正DRC的net，但不一定能修复完，可以一开始多修几次。
2，第一步没修完的话可以把DRC的net 删除了，做eco。这里主要是怎么选到这些net，首先打开error browser （可以在菜单verification下选error browse，在弹出窗口勾选DRC，再选择对应的design cell，注意勾选‘show all views’才能出现design cells）；在error browser 中所有的DRC 都列出来了，可以把所有的DRC error 全选，再在菜单select 下拉中选nets of selected errors，就可以在layout 中把所有的DRC net选上了，接下来就是群秒了~~；最后就是eco 了，route_zrt_eco，就看结果了。

先hihglight后将其删除，再route_zrt_eco -open_net_driven_true

Antenna Violation Fixing

1.方法b为route_opt自动修复antenna effect方法，前提是在route_opt之前：（一定要执行）
set_route_zrt_detail_options–antenna false sourceantenna_rule.tcl
2.方法c是在route_opt之后发现icc提示还有antenna的violation，或physical verification报有一些antenna的violation，可以使用
insert_zrt_diodes
插入Antenna diode cell；

Reducing Critical Area

加通孔

Flow1：PostRouteRedundantViasinsertion

默认情况initial_route运行完成后，insert_zrt_redundant_vias

report_design -physical,查看通孔

Flow2：Concurrent Redundant Via Insertion

icc_shell>set_route_zrt_common_options\
-concurrent_redundant_via_modereserve_space;#默认off icc_shell>set_route_zrt_common_options\
-concurrent_redundant_via_effort_levelhigh;#默认low icc_shell>set_route_zrt_common_options\
-post_detail_route_redundant_via_insertionhigh;#默认off icc_shell>route_opt–……

拉宽线，拉远线

完成绕线后给后面加上

icc_shell>spread_zrt_wires
icc_shell>widen_zrt_wires

outputs_icc.tcl



if {1} { ;# in new icc_shell
	set DATA_DIR ../output_data/v0
	sh mkdir -p  $DATA_DIR
	source ../scripts/rm_setup/icc_setup.tcl 
	source ../scripts/usr_tcl/set_mmmc_libs.tcl
	
	
	set from_mw_cel "$DESIGN_NAME"
		
	sh rm -rf  $DATA_DIR/${DESIGN_NAME}_LIB
	create_mw_lib -tech $TECH_FILE -bus_naming_style {[%d]} -mw_reference_library "$MW_REFERENCE_LIB_DIRS"  $DATA_DIR/${DESIGN_NAME}_LIB
	copy_mw_cel -from_lib ${MW_DESIGN_LIBRARY} -to_lib $DATA_DIR/${DESIGN_NAME}_LIB -from $from_mw_cel -to $DESIGN_NAME

   	set_mw_lib_reference $DATA_DIR/${DESIGN_NAME}_LIB -mw_reference_library "$MW_REFERENCE_LIB_DIRS"
	

	###GDSII
	open_mw_lib $DATA_DIR/${DESIGN_NAME}_LIB
	list_mw_cels
	set_tlu_plus_files -max_tluplus $TLUPLUS_CMAX -min_tluplus $TLUPLUS_CMIN -tech2itf_map $TLUPLUS_MAP
	open_mw_cel $DESIGN_NAME

}

set RESULTS_DIR $DATA_DIR


#######################################
####Outputs Script
#######################################
set enable_page_mode false
##Change Names
change_names -rules verilog -hierarchy
save_mw_cel -as $DESIGN_NAME
#close_mw_cel
#open_mw_cel change_names_icc
#

derive_pg_connection -power_net VDD -power_pin VDD -cells [get_flat_cells *] -reconnect
derive_pg_connection -ground_net VSS -ground_pin VSS -cells [get_flat_cells *] -reconnect



##Verilog
#write_verilog -diode_ports -no_physical_only_cells -pg -supply_statement none $RESULTS_DIR/$DESIGN_NAME.output.pg.v

write_verilog -no_physical_only_cells -supply_statement none $RESULTS_DIR/$DESIGN_NAME.output.pt.v

## For LVS use,the option -no_physical_only_cells is removed
#write_verilog -diode_ports -pg $RESULTS_DIR/$DESIGN_NAME.output.pg.lvs.v

## For Prime Time use,to include DCAP cells for leakage power analysis, add the option -force_output_references


##DEF
write_def -output  $RESULTS_DIR/$DESIGN_NAME.output.def




#############insert filler
remove_stdcell_filler -stdcell

set_keepout_margin  -type hard -all_macros -outer {5 5 5 5}

set decap_fillers "DCAP_HVT"
set fillers "SHFILL1_HVT SHFILL2_HVT SHFILL3_HVT SHFILL64_HVT SHFILL128_HVT"

insert_stdcell_filler -respect_keepout -connect_to_power VDD -connect_to_ground VSS  -cell_with_metal $decap_fillers -cell_with_metal_prefix decap_

insert_stdcell_filler -respect_keepout -connect_to_power VDD -connect_to_ground VSS -cell_with_metal $fillers


##Verilog with filler
##Verilog
#write_verilog -diode_ports -no_physical_only_cells -pg -supply_statement none $RESULTS_DIR/$DESIGN_NAME.output.pg.filler.v

#write_verilog -no_physical_only_cells -pg -supply_statement none $RESULTS_DIR/$DESIGN_NAME.output.pg.dc.filler.v


## For LVS use,the option -no_physical_only_cells is removed
save_mw_cel -as bak
remove_cell *SHFILL* > rm_filler.log
write_verilog -diode_ports -pg $RESULTS_DIR/$DESIGN_NAME.output.pg.lvs.filler.v
close_mw_cel
copy_mw_cel -from bak -to $DESIGN_NAME
open_mw_cel $DESIGN_NAME
remove_mw_cel bak


## For Prime Time use,to include DCAP cells for leakage power analysis, add the option -force_output_references

##DEF
write_def -output  $RESULTS_DIR/$DESIGN_NAME.output.filler.def


##SDC
#set_app_var write_sdc_output_lumped_net_capacitance false
#set_app_var write_sdc_output_net_resistance false
#
#set cur_scenario [current_scenario]
#foreach scenario [all_active_scenarios] {
#  	current_scenario $scenario
#  	write_sdc $RESULTS_DIR/$DESIGN_NAME.$scenario.output.sdc
#};
#current_scenario $cur_scenario


source ../scripts/rm_setup/icc_setup.tcl
source ../scripts/usr_tcl/set_mmmc_libs.tcl


#remove_sdc
#remove_scenario -all
source ../scripts/usr_tcl/set_mmmc_libs.tcl
#source ../scripts/usr_tcl/mmmc_postCTS.tcl


source ../scripts/rm_icc_scripts/common_optimization_settings_icc.tcl 
source ../scripts/rm_icc_scripts/common_placement_settings_icc.tcl 
source ../scripts/rm_icc_scripts/common_cts_settings_icc.tcl 
source ../scripts/rm_icc_scripts/common_post_cts_timing_settings.tcl
source ../scripts/rm_icc_zrt_scripts/common_route_si_settings_zrt_icc.tcl


#extract_rc -coupling_cap
#foreach sc [all_active_scenarios] {
#	current_sc $sc
#	write_parasitics  -format SPEF -output $RESULTS_DIR/$DESIGN_NAME.output.${sc}.spef
#}

##create pg pin
#source ../../scripts_block/usr_tcl/extend_pg_pin.tcl



set_ignored_layers -min_routing_layer M1 -max_routing_layer M6

  ########################################
  #       TIMING DRIVEN METAL FILL       # 
  ########################################
	#-width {m1 0.3 m2 0.3 m3 0.3 m4 0.3 m5 0.3 m6 0.3 m7 0.3} 
	#-min_length {m1 0.3 m2 0.3 m3 0.3 m4 0.3 m5 0.3 m6 0.3 m7 0.3} 
	#-max_length {m1 2 m2 2 m3 2 m4 2 m5 2 m6 2 m7 2} 
    set_extraction_options -real_metalfill_extraction NONE
if {1} {
    insert_metal_filler -routing_space 9 \
	-timing_driven -from_metal 1 -to_metal 6 \
	-stagger {m1 m2 m3 m4 m5 m6 } \
	-width {m1 0.3 m2 0.3 m3 0.3 m4 0.3 m5 0.3 m6 0.3 } \
	-min_length {m1 0.5 m2 0.5 m3 0.5 m5 0.5 m6 0.5 } \
	-max_length {m1 1 m2 2 m3 2 m5 2 m6 2 } 
	#-fill_poly
} else {
	signoff_metal_fill -purge
	set_physical_signoff_options -exec_cmd hercules \
		-fill_runset ../scripts/usr_tcl/rules.fill.9m_saed90.ev
	signoff_metal_fill -select_layers {M1 M2 M3 M4 M5 M6} \
		-output_view signoff_metal_fill.FILL \
		-mode flat 
}

	set_extraction_options -real_metalfill_extraction FLOATING

set RESULTS_DIR $DATA_DIR
##GDSII
#Set options - usually also include a mapping file (-map_layer)
   set_write_stream_options \
	-child_depth 255 \
	-map_layer /library/tech/icc/saed90nm.gdsout.map \
      	-output_filling fill \
       	-output_outdated_fill \
       	-keep_data_type \
	-max_name_length 255 \
	-output_net_name_as_property 1 \
	-output_instance_name_as_property 1 \
	-output_pin {geometry text}

   write_stream -cells $DESIGN_NAME -lib_name $RESULTS_DIR/${DESIGN_NAME}_LIB -format gds $RESULTS_DIR/$DESIGN_NAME.gds


###############
#	set ns [get_net_shapes -of [get_nets -all {VSS VDD}] -f layer==M7]
#	convert_wire_to_pin -net_names {VSS VDD} $ns
#  	remove_placement_blockage -all
#  	remove_routing_blockage *
#  	remove_route_guide -all
#  	save_mw_cel
#
#	##
#
#	set_ignored_layers -min_routing_layer M1 -max_routing_layer M8
#	create_macro_fram ;#-identify_macro_pin_by_pin_text
#  	extract_zrt_hier_antenna_property -cell_name $DESIGN_NAME

加入DCAP后