hdlbites练习11

module top_module (
    input clk,    // Clocks are used in sequential circuits
    input d,
    output reg q );//

    always@( posedge clk )
        begin
           q <= d; 
        end

endmodule

Create 8 D flip-flops. All DFFs should be triggered by the positive edge of clk.

module top_module (
    input clk,
    input [7:0] d,
    output [7:0] q
);

    always@(posedge clk)
        begin
            q <= d;
        end
endmodule

创建具有有效高同步复位功能的 8D 触发器。所有 DFF 都应由 clk 的正边触发。

module top_module (
    input clk,
    input reset,            // Synchronous reset
    input [7:0] d,
    output [7:0] q
);

    always@(posedge clk)
        begin
            if(reset)
                begin
                   q <= 8'b0; 
                end
            else
                begin
                    q <= d;
                end
        end
endmodule

创建具有有效高同步复位功能的 8D 触发器。触发器必须重置为0x34而不是零。所有 DFF 都应由 clk 的负边触发。

module top_module (
    input clk,
    input reset,
    input [7:0] d,
    output [7:0] q
);
    
    always@(negedge clk)
        begin
            if(reset)
                begin
                   q <= 8'h34; 
                end
            else
                begin
                    q <= d;
                end
        end

endmodule

创建具有主动高异步复位功能的 8D 触发器。所有 DFF 都应由 clk 的正边触发。

module top_module (
    input clk,
    input areset,   // active high asynchronous reset
    input [7:0] d,
    output [7:0] q
);

    always@(posedge clk or posedge areset)
        begin
            if(areset)
                begin
                   q <= 8'b0; 
                end
            else
                begin
                   q <= d; 
                end
        end
    
endmodule

创建 16 D 人字拖。有时只修改一组触发器的一部分很有用。使能字节的输入控制是否应在该周期内写入 16 个寄存器中的每个字节。byteena[1] 控制上字节 d[15：8]，而 byteena[0] 控制下字节 d[7：0]。

module top_module (
    input clk,
    input resetn,
    input [1:0] byteena,
    input [15:0] d,
    output [15:0] q
);

    always@(posedge clk)
        begin
            if(~resetn)
                begin
                     q <= 16'b0; 
                end
            else
                begin
                    if(byteena[1])
                        begin
                            q[15:8] <= d[15:8]; 
                        end
                    if(byteena[0])
                        begin
                            q[7:0] <= d[7:0];
                        end
                end
        end
    
endmodule

module top_module (
    input d, 
    input ena,
    output q);

    always@(*)
        begin
            if(ena)
                begin
                   q <= d; 
                end
        end
endmodule

module top_module (
    input clk,
    input d, 
    input ar,   // asynchronous reset
    output q);

    always@(posedge clk or posedge ar)
        begin
            if(ar)
                begin
                   q <= 1'b0; 
                end
            else
                begin
                   q <= d; 
                end
        end
endmodule

module top_module (
    input clk,
    input d, 
    input r,   // synchronous reset
    output q);
    
    always@(posedge clk) begin
        if(r)
            q<=1'b0;
        else
            q<=d;
    end

endmodule

module top_module (
    input clk,
    input in, 
    output out);

    reg d;
    always@(posedge clk)
        begin
            d = out^in;
            out <= d;
        end
endmodule

module top_module (
	input clk,
	input L,
	input r_in,
	input q_in,
	output reg Q);

    wire d;
    
    assign d = L?r_in:q_in;
    always@(posedge clk)
        begin
            Q <= d; 
        end
endmodule

module top_module (
    input clk,
    input w, R, E, L,
    output Q
);
    
    wire d,D;
    assign d = E?w:Q;
    assign D = L?R:d;
    always@(posedge clk)
        begin
            Q <= D;
        end

endmodule

module top_module (
    input clk,
    input x,
    output z
); 

    wire d0,d1,d2,q0,q1,q2;
    assign d0 = x^q0;
    assign d1 = x&(~q1);
    assign d2 = x|(~q2);
    assign z = ~(q0|q1|q2);
    always@(posedge clk)
        begin
            q0 <= d0;
            q1 <= d1;
            q2 <= d2;
        end
endmodule

module top_module (
    input clk,
    input j,
    input k,
    output Q); 

    always@(posedge clk)
        begin
            Q <= (j&(~Q))|((~k)&Q); 
        end
endmodule

module top_module (
    input clk,
    input [7:0] in,
    output [7:0] pedge
);

    reg [7:0] temp_in;
    
    always @(posedge clk) begin
        temp_in <= in;
        pedge <= ~temp_in & in;
    end
    
endmodule