FIR滤波器的设计

最新推荐文章于 2025-06-04 22:09:14 发布

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最新推荐文章于 2025-06-04 22:09:14 发布

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本文链接：https://blog.csdn.net/qq_71663825/article/details/137754392

FIR(Finite Impulse Response)滤波器：有限长单位冲激响应滤波器，又称为非递归型滤波器，是数字信号处理系统中最基本的元件，它可以在保证任意幅频特性的同时具有严格的线性相频特性，同时其单位抽样响应是有限长的，因而滤波器是稳定的系统。因此，FIR滤波器在通信、图像处理、模式识别等领域都有着广泛的应用。

该滤波器的系数为G(Z)=0.48301+0.8365Z +0.2241Z2-0.1294Z-3。若将系数变换成8位(加上符号位)精度模G(Z)=124/256+2147/256+57Z--/256-33Z-3/256，因此Y(n)=124 X(n)/256+214X(n-1)/256+57X(n-2)/256-33X(n-3)/256。

顶层程序

--DTFIB.VHD（顶层文件）
LIBRARY LPM;
USE LPM.LPM_COMPONENTS.ALL;
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;

ENTITY DTFIR IS
  PORT(K:IN STD_LOGIC;
       CLK:IN STD_LOGIC;
		 CLK2:IN STD_LOGIC;
		 COM:OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
		 SEG:OUT STD_LOGIC_VECTOR(7 DOWNTO 0));
END ENTITY DTFIR;

ARCHITECTURE ART OF DTFIR IS
  COMPONENT KG IS
    PORT(CLK:IN STD_LOGIC;
         K:IN STD_LOGIC;
		   TIMES:OUT STD_LOGIC);
    END COMPONENT KG;
  COMPONENT CLKGEN IS
    PORT(CLK: IN STD_LOGIC;
         NEWCLK: OUT STD_LOGIC);
	  
    END COMPONENT CLKGEN;	 
  COMPONENT KZSR IS
    PORT(CLK:IN STD_LOGIC;
         XOUT:OUT STD_LOGIC_VECTOR(8 DOWNTO 0);
		   LOAD:OUT STD_LOGIC;
		   COUT:OUT STD_LOGIC_VECTOR(8 DOWNTO 0));
	  
    END COMPONENT KZSR;
  COMPONENT FIR IS
    GENERIC(W1:INTEGER:=9;
			   W2:INTEGER:=18;
			   W3:INTEGER:=19;
			   W4:INTEGER:=11;
			   L:INTEGER:=4;
			   MPIPE:INTEGER:=3);
    PORT(CLK,LOAD_X:IN STD_LOGIC;
		   X_IN,C_IN:IN STD_LOGIC_VECTOR(W1-1 DOWNTO 0);
		   Y_OUT:OUT STD_LOGIC_VECTOR(W4-1 DOWNTO 0));  
    END COMPONENT FIR;
	 
  COMPONENT XSKZQ IS
      PORT (ABCD:IN STD_LOGIC_VECTOR(10 DOWNTO 0);
            G,S,B,Q:OUT STD_LOGIC_VECTOR(3 DOWNTO 0));  
     END COMPONENT XSKZQ;
	 
  COMPONENT CTRLS IS
    PORT(CLK: IN STD_LOGIC;      
         SEL: OUT STD_LOGIC_VECTOR(2 DOWNTO 0));
    END COMPONENT CTRLS;
  COMPONENT DISPLAY IS
    PORT(SEL: IN STD_LOGIC_VECTOR(2 DOWNTO 0);
         G,S,B,Q: IN STD_LOGIC_VECTOR(3 DOWNTO 0);
         COM: OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
         SEG: OUT STD_LOGIC_VECTOR(7 DOWNTO 0));
    END COMPONENT DISPLAY;
  SIGNAL CK:STD_LOGIC; 
  SIGNAL S0,S1,S2:STD_LOGIC; 
  SIGNAL SD:STD_LOGIC_VECTOR(8 DOWNTO 0);
  SIGNAL SL:STD_LOGIC_VECTOR(8 DOWNTO 0);
  SIGNAL SM:STD_LOGIC_VECTOR(10 DOWNTO 0);
  SIGNAL G,S,B,Q:STD_LOGIC_VECTOR(3 DOWNTO 0);
  S