HDLbits: Mux9to1v

原创已于 2023-10-12 20:50:00 修改 · 164 阅读

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于 2023-09-27 16:55:23 首次发布

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该代码描述了一个16位的9-1多路选择器模块，根据输入的selector选择不同的输入信号，未选中的输出位设置为全1。使用case语句和procedural块实现了组合逻辑电路。

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题目：Create a 16-bit wide, 9-to-1 multiplexer. sel=0 chooses a, sel=1 chooses b, etc. For the unused cases (sel=9 to 15), set all output bits to '1'.

我的答案：

module top_module( 
    input [15:0] a, b, c, d, e, f, g, h, i,
    input [3:0] sel,
    output [15:0] out );
    always@(*)
        case(sel)
            4'b0000: out = a;
            4'b0001: out = b;
            4'b0010: out = c;
            4'b0011: out = d;
            4'b0100: out = e;
            4'b0101: out = f;
            4'b0110: out = g;
            4'b0111: out = h;
            4'b1000: out = i;
            4'b1001: out = 16'b1111111111111111;
            4'b1010: out = 16'b1111111111111111;
            4'b1011: out = 16'b1111111111111111;
            4'b1100: out = 16'b1111111111111111;
            4'b1101: out = 16'b1111111111111111;
            4'b1110: out = 16'b1111111111111111;
            4'b1111: out = 16'b1111111111111111;
        endcase
endmodule

网站答案：

module top_module (
	input [15:0] a,
	input [15:0] b,
	input [15:0] c,
	input [15:0] d,
	input [15:0] e,
	input [15:0] f,
	input [15:0] g,
	input [15:0] h,
	input [15:0] i,
	input [3:0] sel,
	output logic [15:0] out
);

	// Case statements can only be used inside procedural blocks (always block)
	// This is a combinational circuit, so use a combinational always @(*) block.
	always @(*) begin
		out = '1;		// '1 is a special literal syntax for a number with all bits set to 1.
						// '0, 'x, and 'z are also valid.
						// I prefer to assign a default value to 'out' instead of using a
						// default case.
		case (sel)
			4'h0: out = a;
			4'h1: out = b;
			4'h2: out = c;
			4'h3: out = d;
			4'h4: out = e;
			4'h5: out = f;
			4'h6: out = g;
			4'h7: out = h;
			4'h8: out = i;
		endcase
	end
	
endmodule