FPGA project - AD7606

I use AD7606 to catch 8 ch sigals.

`timescale 1ns / 1ps

module ad7606(
    input                   clk                 ,       //clock input
    input                   rst_n               ,       //reset input, low active
    input                   ad_busy             ,       //ad7606 convert busy
    input                   first_data          ,       //ad7606 first data
    input                   sign                ,       //1:module active 0:module fail
    input   [15:0]          ad_data             ,       //ad7606 data input
    
    output                  ad_data_valid       ,       //ad7606 data finish convert sign
    output  [2:0]           ad_os               ,       //oversampling mode select
    
    output  reg             module_init         ,       //module init finish
    output  reg             ad_cs               ,       //ad7606 AD cs
    output  reg             ad_rd               ,       //ad7606 AD rd
    output  reg             ad_reset            ,       //ad7606 AD reset
    output  reg             ad_convstab         ,       //ad7606 AD convert start
    
    output  reg [15:0]      ad_ch1              ,       //ad7606 convert data ch1
    output  reg [15:0]      ad_ch2              ,       //ad7606 convert data ch2
    output  reg [15:0]      ad_ch3              ,       //ad7606 convert data ch3
    output  reg [15:0]      ad_ch4              ,       //ad7606 convert data ch4
    output  reg [15:0]      ad_ch5              ,       //ad7606 convert data ch5
    output  reg [15:0]      ad_ch6              ,       //ad7606 convert data ch6
    output  reg [15:0]      ad_ch7              ,       //ad7606 convert data ch7
    output  reg [15:0]      ad_ch8                      //ad7606 convert data ch8
);

//macro definition parameters
parameter                  cycle_time      =   2500    ;       //a convert cycle set

//state machine code
localparam                  IDLE            =   4'd0    ;      //init and wait state
localparam                  AD_CONV         =   4'd1    ;      //posedge edge start convert
localparam                  Wait_1          =   4'd2    ;      //wait finish convert
localparam                  Wait_busy       =   4'd3    ;      //check convert finish sign
localparam                  READ_CH1        =   4'd4    ;      //data ch1 read
localparam                  READ_CH2        =   4'd5    ;      //data ch2 read
localparam                  READ_CH3        =   4'd6    ;      //data ch3 read
localparam                  READ_CH4        =   4'd7    ;      //data ch4 read
localparam                  READ_CH5        =   4'd8    ;      //data ch5 read
localparam                  READ_CH6        =   4'd9    ;      //data ch6 read
localparam                  READ_CH7        =   4'd10   ;      //data ch7 read
localparam                  READ_CH8        =   4'd11   ;      //data ch8 read
localparam                  READ_DONE       =   4'd12   ;      //data deliver

//reg define
reg [3:0]                   state               ;       //current state reg
reg [5:0]                   i                   ;       //state change count
reg [15:0]                  cycle_cnt           ;       //convert data count
reg [7:0]                   rst_