Verilog有限状态机设计

摩尔型有限状态机设计模5计数器

module fsm1(input clk, clr,
            output reg [2:0] qout,
            output reg z);
    always @(posedge clk or posedge clr)
    begin if (clr) qout <= 0;
    else case(qout)
    3'b000:begin qout<= 3'b001; z<=1'b0;end
    3'b001:begin qout<= 3'b010; z<=1'b0;end
    3'b010:begin qout<= 3'b100; z<=1'b1;end
    3'b100:begin qout<= 3'b000; z<=1'b0;end
    default :begin qout <= 3'b000; z<=1'b0;end
    endcase
    end
endmodule