JTAG：
Joint Test Action Group
联合测试行动小组的简称，成立于1980年，目的是为了制订统一的芯片测试方法---边界扫描测试，该测试标准在1990年被IEEE（电气与电子工程师协会）采纳为标准
IEEE Standard 1149.1-1990
，并保留了JTAG的名字，也称为JTAG标准，后面该标准不断发展和完善。
相应的标准文档：http://fiona.dmcs.pl/~cmaj/JTAG/JTAG_IEEE-Std-1149.1-2001.pdf
其他参考文档：
The IEEE standard defines the Test Access Port (TAP
，由4-5个引脚组成), the TAP controller（在IC芯片内部，是一个有限状态机）, a Instruction Register, and a number of Data Registers.
JTAG Chip Architecture
- q A set of four dedicated test pins — Test Data In (TDI), Test Mode Select (TMS), Test Clock (TCK), Test Data Out (TDO) — and one optional test pin Test Reset (TRST*). These pins are collectively referred to as the Test Access Port (TAP).
- q A boundary-scan cell on the device primary input and primary output pins of a device, connected internally to form a serial boundary-scan register (Boundary Scan).
- q A finite-state machine TAP controller with inputs TCK, TMS, and TRST*.
- q An n-bit (n ≥ 2) Instruction Register (IR), holding the current instruction.
- q A 1-bit bypass register (Bypass).
- q An optional 32-bit Identification Register (Ident) capable of being loaded with a permanent device identification code.
JTAG Interface
The physical JTAG interface, or test access port (TAP) consists of four mandatory signals and one optional asynchronous reset signal. Table 1 below summarizes the JTAG TAP signals.
TAP Controller
The TAP controller as defined by the IEEE-1149.1 standard uses a 16-state finite state machine controlled by a test clock (TCK) and test mode select (TMS) signals. Transitions are determined by the state of TMS on the rising edge of TCK.
Two analogous paths through the state machine are used to capture and/or update data by scanning through the instruction register (IR) or through a data register (DR). The JTAG state machine is depicted in Figure 10 below.
JTAG instruction register
The IR mu
st be at least two-bits long (to allow coding of the four mandatory instructions —
Bypass
,
Sample, Preload
,
Extest
— but the maximum length of the IR is not defined. In capture mode, the two least
significant bits must capture a 01 pattern
The instruction
is used to select the test to be performed or the test data register to be accessed or both.
因为指令寄存器只有一个，状态机select-IR-scan首先更新指令寄存器的内容，然后状态机转到select-DR-scan, 根据指令寄存器的内容解码形成scan path，即连接TD1
à
Data register
à
TDO, 然后更新data register的内容。
JTAG data register
IEEE-1149.1
标准规定必须实现的数据寄存器有：边界扫描寄存器（BSR），旁路寄存器和识别码寄存器。其他数据寄存器可能存在，但不是JTAG标准所需的部分。
- BSR–这是主要测试的数据寄存器。它被用来把数据从器件I/O针脚处移出和移入。
- BYPASS这是一个把信息从TDI传到TDO的单位寄存器。它可以用最小的系统开销来测试电路中其他的器件。
- IDCODES–这个寄存器含有器件的识别码和版本序号。这个信息可以使器件和它的边界扫描描述语言（BSDL）文件相关联这个文件含有器件边界扫描配置的详细情况。
Capture-IR State
In the Capture-IR state, the two LSBs of the Instruction register are loaded with the value 012, and the upper MSBs are loaded with implementation-dependent values. Both values are loaded on the rising edge of TCK.
Shift-IR State
In the Shift-IR state, the LSB of the Instruction register is output on TDO on the falling edge of TCK. The Instruction register is shifted one position from MSB to LSB on the rising edge of TCK, with the MSB shifted in from TDI. The value in the Instruction register does not take effect until the Update-IR state.
Update-IR State
In the Update-IR state, the value in the Instruction register takes effect on the rising or falling edge of TCK.
Capture-DR State
In the Capture-DR state, the value of the selected data register(s) is captured on the rising edge of TCK for shifting out in the Shift-DR state. The Capture-DR state reads the data, in order to output this read value in the Shift-DR state.
The Instruction register controls the selection of the following data register(s): Bypass, Device ID, Implementation, EJTAG Control, Address, and Data register(s).
Shift-DR State
In the Shift-DR state, the LSB of the selected data register(s) is output on TDO on the falling edge of TCK. The selected data register(s) is shifted one position from MSB to LSB on the rising edge of TCK, with TDI shifted in at the MSB. The value(s) shifted into the register(s) does not take effect until the Update-DR state.
Update-DR State
In the Update-DR state, the update of the selected data register(s) with the value from the Shift-DR state occurs on the falling or rising edge of TCK. This update writes the selected register(s).
JTAG Instructions
IEEE-1149.1
标准规定必须实现的指令有：
EXTEST
The EXTEST instruction is used to perform interconnect testing. When the EXTEST instruction is used, the mandatory boundary-scan register is connected between TDI and TDO and the device is placed in an “external” test mode. In this mode, boundary-scan output cells will drive test data onto the device pins and input cells will capture data from device pins—this is the main instruction used for boundary-scan testing.
SAMPLE/PRELOAD
The SAMPLE/PRELOAD instruction is similar to EXTEST, but allows the boundary-scan device to remain in mission/functional mode while still connecting the boundary-scan register to TDI and TDO. When the SAMPLE/PRELOAD instruction is used, the boundary-scan register is accessible through data scans while the device remains functional
. This is also useful for preloading data into the boundary-scan register without interrupting the device’s functional behavior, prior to executing the EXTEST instruction.
BYPASS
When the BYPASS instruction is used, TDI and TDO are connected to a
single-bit register that bypasses the longer boundary-scan register of the device—hence the name. BYPASS is very useful for reducing the overall length of a boundary-scan chain by eliminating devices that do not need to be involved in the current action. D
evices that are given the BYPASS instruction remain in mission/functional mode while allowing serial data to flow through to the next device in the chain.
边界扫描
JTAG定义最初的目的是为了边界扫描
Primarily, boundary-scan cells must be provided on all device input and output signal pins, with the exception of Power and Ground.
It has four modes of operation: normal, update, capture, and serial shift.
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