vitis HLS 在进行C simulation时遇到工程csim/build/csim.exe not found 报错的问题排查

本文指导如何解析Csim编译错误,重点关注头文件问题及build链接阶段的报错。通过_csim.log定位问题,学会清理缓存和检查日志以解决csim.exe未找到等常见问题。

摘要生成于 C知道 ,由 DeepSeek-R1 满血版支持, 前往体验 >

在进行HLS设计学习时,想对写好的东西进行C代码模拟,但最后提示存在错误,如下:
C仿真问题
查看错误信息的话,只有抽象的ERROR: [SIM 211-100] CSim file generation failed: compilation error(s).这种提示,并不能定位到具体问题。
在这里插入图片描述
这是因为之前的开发思路局限了,认为工作的错误都会全部集中在错误栏,从而一头雾水,其实在C simulation时其所有警告和错误都会在_csim.log中体现,图中第5行则表明了本质错误为找不到头文件这种简单的问题。
在这里插入图片描述
而标题中遇到工程csim/build/csim.exe not found 报错这个情况,是由于编译没有问题而在链接link过程中出现问题的报错,报错信息会显得更加隐晦,但只要在日志中定位问题就可以解决。在这里插入图片描述
另外,在C simulation的运行如果出错了的话,有可能存在文件明明改好了但仍然报一样的错误的问题,这时候最好在运行前勾选Clean build选项,如果仍然不行的话,请注意看弹出的日志文件,有时这个日志文件并不会自动更新,你的运行也许已经成功了但你只是看到了之前错误的日志,可以试图删除日志后再运行以确认。
在这里插入图片描述

Starting C synthesis ... Starting C simulation ... D:/vitis202302/Vitis_HLS/2023.2/bin/vitis_hls.bat G:/HLS_Test/axi_test/axi_test/axi_test/csim.tcl INFO: [HLS 200-10] Running 'D:/vitis202302/Vitis_HLS/2023.2/bin/unwrapped/win64.o/vitis_hls.exe' INFO: [HLS 200-10] For user 'HP' on host 'desktop-qjs3vb7' (Windows NT_amd64 version 6.2) on Fri Jul 18 15:20:31 +0800 2025 INFO: [HLS 200-10] In directory 'G:/HLS_Test/axi_test' INFO: [HLS 200-2053] The vitis_hls executable is being deprecated. Consider using vitis-run --mode hls --tcl Sourcing Tcl script 'G:/HLS_Test/axi_test/axi_test/axi_test/csim.tcl' INFO: [HLS 200-1510] Running: source G:/HLS_Test/axi_test/axi_test/axi_test/csim.tcl INFO: [HLS 200-1510] Running: open_project axi_test INFO: [HLS 200-10] Opening project 'G:/HLS_Test/axi_test/axi_test'. INFO: [HLS 200-1510] Running: add_files axi_interfaces.c INFO: [HLS 200-10] Adding design file 'axi_interfaces.c' to the project INFO: [HLS 200-1510] Running: add_files -tb axi_interfaces_test.c INFO: [HLS 200-10] Adding test bench file 'axi_interfaces_test.c' to the project INFO: [HLS 200-1510] Running: open_solution axi_test -flow_target vivado INFO: [HLS 200-10] Opening solution 'G:/HLS_Test/axi_test/axi_test/axi_test'. INFO: [SYN 201-201] Setting up clock 'default' with a period of 5ns. INFO: [HLS 200-1611] Setting target device to 'xcvu11p-flga2577-1-e' INFO: [HLS 200-1505] Using flow_target 'vivado' Resolution: For help on HLS 200-1505 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2023.2%20English&url=ug1448-hls-guidance&resourceid=200-1505.html INFO: [HLS 200-1510] Running: set_part xcvu11p-flga2577-1-e INFO: [HLS 200-1510] Running: create_clock -period 5 -name default INFO: [SYN 201-201] Setting up clock 'default' with a period of 5ns. INFO: [HLS 200-1510] Running: csim_design -quiet INFO: [SIM 211-2] *************** CSIM start *************** INFO: [SIM 211-4] CSIM will launch GCC as the compiler. INFO: [HLS 200-2036] Building debug C Simulation binaries Compiling(apcc) ../../../../axi_interfaces_test.c in debug mode INFO: [HLS 200-10] Running 'D:/vitis202302/Vitis_HLS/2023.2/bin/unwrapped/win64.o/apcc.exe' INFO: [HLS 200-10] For user 'HP' on host 'desktop-qjs3vb7' (Windows NT_amd64 version 6.2) on Fri Jul 18 15:20:34 +0800 2025 INFO: [HLS 200-10] In directory 'G:/HLS_Test/axi_test/axi_test/axi_test/csim/build' ../../../../axi_interfaces_test.c:42:10: warning: implicit declaration of function 'system' is invalid in C99 [-Wimplicit-function-declaration] retval = system("diff --brief -w result.dat result.golden.dat"); ^ 1 warning generated. ../../../../axi_interfaces_test.c:42:10: warning: implicit declaration of function 'system' is invalid in C99 [-Wimplicit-function-declaration] retval = system("diff --brief -w result.dat result.golden.dat"); ^ 1 warning generated. INFO: [APCC 202-3] Tmp directory is G:/HLS_Test/axi_test/axi_test/axi_test/csim/build/apcc_db_HP/231284131701203 INFO: [APCC 202-1] APCC is done. INFO: [HLS 200-112] Total CPU user time: 1 seconds. Total CPU system time: 0 seconds. Total elapsed time: 0.741 seconds; peak allocated memory: 8.262 MB. Compiling(apcc) ../../../../axi_interfaces.c in debug mode INFO: [HLS 200-10] Running 'D:/vitis202302/Vitis_HLS/2023.2/bin/unwrapped/win64.o/apcc.exe' INFO: [HLS 200-10] For user 'HP' on host 'desktop-qjs3vb7' (Windows NT_amd64 version 6.2) on Fri Jul 18 15:20:36 +0800 2025 INFO: [HLS 200-10] In directory 'G:/HLS_Test/axi_test/axi_test/axi_test/csim/build' INFO: [APCC 202-3] Tmp directory is G:/HLS_Test/axi_test/axi_test/axi_test/csim/build/apcc_db_HP/81684133866848 INFO: [APCC 202-1] APCC is done. INFO: [HLS 200-112] Total CPU user time: 1 seconds. Total CPU system time: 0 seconds. Total elapsed time: 0.722 seconds; peak allocated memory: 11.082 MB. Generating csim.exe diff: result.golden.dat: No such file or directory Test failed !!! @E Simulation failed: Function 'main' returns nonzero value '1'. ERROR: [SIM 211-100] 'csim_design' failed: nonzero return value. INFO: [SIM 211-3] *************** CSIM finish *************** INFO: [HLS 200-111] Finished Command csim_design CPU user time: 0 seconds. CPU system time: 0 seconds. Elapsed time: 5.089 seconds; current allocated memory: 0.633 MB. 4 while executing "source G:/HLS_Test/axi_test/axi_test/axi_test/csim.tcl" invoked from within "hls::main G:/HLS_Test/axi_test/axi_test/axi_test/csim.tcl" ("uplevel" body line 1) invoked from within "uplevel 1 hls::main {*}$newargs" (procedure "hls_proc" line 16) invoked from within "hls_proc [info nameofexecutable] $argv" INFO: [HLS 200-112] Total CPU user time: 2 seconds. Total CPU system time: 0 seconds. Total elapsed time: 7.19 seconds; peak allocated memory: 193.797 MB. Finished C simulation.
07-19
Starting C simulation ... D:/vitis202302/Vitis_HLS/2023.2/bin/vitis_hls.bat G:/vitis2023_project/SmoothProfileOnXAxisMean_NoGray/solution2/csim.tcl INFO: [HLS 200-10] Running 'D:/vitis202302/Vitis_HLS/2023.2/bin/unwrapped/win64.o/vitis_hls.exe' INFO: [HLS 200-10] For user 'HP' on host 'desktop-qjs3vb7' (Windows NT_amd64 version 6.2) on Tue Jul 22 15:29:28 +0800 2025 INFO: [HLS 200-10] In directory 'G:/vitis2023_project' INFO: [HLS 200-2053] The vitis_hls executable is being deprecated. Consider using vitis-run --mode hls --tcl Sourcing Tcl script 'G:/vitis2023_project/SmoothProfileOnXAxisMean_NoGray/solution2/csim.tcl' INFO: [HLS 200-1510] Running: source G:/vitis2023_project/SmoothProfileOnXAxisMean_NoGray/solution2/csim.tcl INFO: [HLS 200-1510] Running: open_project SmoothProfileOnXAxisMean_NoGray INFO: [HLS 200-10] Opening project 'G:/vitis2023_project/SmoothProfileOnXAxisMean_NoGray'. INFO: [HLS 200-1510] Running: set_top SmoothProfileOnXAxisMean INFO: [HLS 200-1510] Running: add_files SmoothProfileOnXAxisMean.cpp WARNING: [HLS 200-40] Cannot find design file 'SmoothProfileOnXAxisMean.cpp' INFO: [HLS 200-1510] Running: add_files SmoothProfileOnXAxisMean_NoGray/src/SmoothProfileOnXAxisMean.h INFO: [HLS 200-10] Adding design file 'SmoothProfileOnXAxisMean_NoGray/src/SmoothProfileOnXAxisMean.h' to the project INFO: [HLS 200-1510] Running: add_files -tb SmoothProfileOnXAxisMean_NoGray/src/SmoothProfileOnXAxisMean_test.cpp -cflags -Wno-unknown-pragmas INFO: [HLS 200-10] Adding test bench file 'SmoothProfileOnXAxisMean_NoGray/src/SmoothProfileOnXAxisMean_test.cpp' to the project INFO: [HLS 200-1510] Running: open_solution solution2 -flow_target vivado INFO: [HLS 200-10] Opening solution 'G:/vitis2023_project/SmoothProfileOnXAxisMean_NoGray/solution2'. INFO: [SYN 201-201] Setting up clock 'default' with a period of 5ns. INFO: [SYN 201-201] Setting up clock 'default' with an uncertainty of 0.35ns. INFO: [HLS 200-1611] Setting target device to 'xcku060-ffva1156-2-e' INFO: [HLS 200-1505] Using flow_target 'vivado' Resolution: For help on HLS 200-1505 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2023.2%20English&url=ug1448-hls-guidance&resourceid=200-1505.html INFO: [HLS 200-1464] Running solution command: config_export -display_name=SmoothProfileOnXAxisMean INFO: [HLS 200-1464] Running solution command: config_export -format=ip_catalog INFO: [HLS 200-1464] Running solution command: config_export -library=KU060_200M_II1_NoGray_WIN33_250721 INFO: [HLS 200-1464] Running solution command: config_export -output=D:/HLS/SmoothProfileOnXAxisMean INFO: [HLS 200-1464] Running solution command: config_export -rtl=verilog INFO: [HLS 200-1464] Running solution command: config_export -vendor=WEIGUO INFO: [HLS 200-1464] Running solution command: config_export -version=2.5 INFO: [HLS 200-1464] Running solution command: config_cosim -tool=xsim INFO: [HLS 200-1510] Running: set_part xcku060-ffva1156-2-e INFO: [HLS 200-1510] Running: create_clock -period 5 -name default INFO: [HLS 200-1510] Running: config_export -display_name SmoothProfileOnXAxisMean -format ip_catalog -library KU060_200M_II1_NoGray_WIN33_250721 -output D:/HLS/SmoothProfileOnXAxisMean -rtl verilog -vendor WEIGUO -version 2.5 INFO: [HLS 200-1510] Running: config_cosim -tool xsim INFO: [HLS 200-1510] Running: set_clock_uncertainty 0.35 INFO: [HLS 200-1510] Running: source ./SmoothProfileOnXAxisMean_NoGray/solution2/directives.tcl INFO: [HLS 200-1510] Running: set_directive_top -name SmoothProfileOnXAxisMean SmoothProfileOnXAxisMean INFO: [HLS 200-1510] Running: csim_design -quiet INFO: [SIM 211-2] *************** CSIM start *************** INFO: [SIM 211-4] CSIM will launch GCC as the compiler. INFO: [HLS 200-2036] Building debug C Simulation binaries Compiling ../../../src/SmoothProfileOnXAxisMean_test.cpp in debug mode Generating csim.exe Makefile.rules:317: recipe for target 'csim.exe' failed In file included from D:/vitis202302/Vitis_HLS/2023.2/include/floating_point_v7_1_bitacc_cmodel.h:150:0, from D:/vitis202302/Vitis_HLS/2023.2/include/hls_fpo.h:140, from D:/vitis202302/Vitis_HLS/2023.2/include/etc/hls_half_fpo.h:19, from D:/vitis202302/Vitis_HLS/2023.2/include/hls_half.h:26, from D:/vitis202302/Vitis_HLS/2023.2/include/etc/ap_private.h:52, from D:/vitis202302/Vitis_HLS/2023.2/include/etc/ap_common.h:666, from D:/vitis202302/Vitis_HLS/2023.2/include/ap_int.h:10, from ../../../src/SmoothProfileOnXAxisMean.h:3, from ../../../src/SmoothProfileOnXAxisMean_test.cpp:3: D:/vitis202302/Vitis_HLS/2023.2/include/gmp.h:58:0: warning: "__GMP_LIBGMP_DLL" redefined #define __GMP_LIBGMP_DLL 0 In file included from D:/vitis202302/Vitis_HLS/2023.2/include/hls_fpo.h:140:0, from D:/vitis202302/Vitis_HLS/2023.2/include/etc/hls_half_fpo.h:19, from D:/vitis202302/Vitis_HLS/2023.2/include/hls_half.h:26, from D:/vitis202302/Vitis_HLS/2023.2/include/etc/ap_private.h:52, from D:/vitis202302/Vitis_HLS/2023.2/include/etc/ap_common.h:666, from D:/vitis202302/Vitis_HLS/2023.2/include/ap_int.h:10, from ../../../src/SmoothProfileOnXAxisMean.h:3, from ../../../src/SmoothProfileOnXAxisMean_test.cpp:3: D:/vitis202302/Vitis_HLS/2023.2/include/floating_point_v7_1_bitacc_cmodel.h:142:0: note: this is the location of the previous definition #define __GMP_LIBGMP_DLL 1 obj/SmoothProfileOnXAxisMean_test.o: In function `main': G:\vitis2023_project\SmoothProfileOnXAxisMean_NoGray\solution2\csim\build/../../../src/SmoothProfileOnXAxisMean_test.cpp:59: undefined reference to `SmoothProfileOnXAxisMean(hls::stream<float, 0>&, hls::stream<float, 0>&, ap_uint<6>, float)' collect2.exe: error: ld returned 1 exit status make: *** [csim.exe] Error 1 ERROR: [SIM 211-100] 'csim_design' failed: compilation error(s). INFO: [SIM 211-3] *************** CSIM finish *************** INFO: [HLS 200-111] Finished Command csim_design CPU user time: 0 seconds. CPU system time: 0 seconds. Elapsed time: 2.536 seconds; current allocated memory: 0.371 MB. 4 while executing "source G:/vitis2023_project/SmoothProfileOnXAxisMean_NoGray/solution2/csim.tcl" invoked from within "hls::main G:/vitis2023_project/SmoothProfileOnXAxisMean_NoGray/solution2/csim.tcl" ("uplevel" body line 1) invoked from within "uplevel 1 hls::main {*}$newargs" (procedure "hls_proc" line 16) invoked from within "hls_proc [info nameofexecutable] $argv" INFO: [HLS 200-112] Total CPU user time: 1 seconds. Total CPU system time: 0 seconds. Total elapsed time: 4.239 seconds; peak allocated memory: 199.672 MB. Finished C simulation.
07-23
Starting C simulation ... D:/vitis202302/Vitis_HLS/2023.2/bin/vitis_hls.bat G:/vitis2023_project/SmoothProfileOnXAxisMean_NoGray_liangjing/SmoothProfileOnXAxisMean_NoGray/SmoothProfileOnXAxisMean_NoGray/csim.tcl INFO: [HLS 200-10] Running 'D:/vitis202302/Vitis_HLS/2023.2/bin/unwrapped/win64.o/vitis_hls.exe' INFO: [HLS 200-10] For user 'HP' on host 'desktop-qjs3vb7' (Windows NT_amd64 version 6.2) on Tue Jul 22 17:03:51 +0800 2025 INFO: [HLS 200-10] In directory 'G:/vitis2023_project/SmoothProfileOnXAxisMean_NoGray_liangjing' INFO: [HLS 200-2053] The vitis_hls executable is being deprecated. Consider using vitis-run --mode hls --tcl Sourcing Tcl script 'G:/vitis2023_project/SmoothProfileOnXAxisMean_NoGray_liangjing/SmoothProfileOnXAxisMean_NoGray/SmoothProfileOnXAxisMean_NoGray/csim.tcl' INFO: [HLS 200-1510] Running: source G:/vitis2023_project/SmoothProfileOnXAxisMean_NoGray_liangjing/SmoothProfileOnXAxisMean_NoGray/SmoothProfileOnXAxisMean_NoGray/csim.tcl INFO: [HLS 200-1510] Running: open_project SmoothProfileOnXAxisMean_NoGray INFO: [HLS 200-10] Opening project 'G:/vitis2023_project/SmoothProfileOnXAxisMean_NoGray_liangjing/SmoothProfileOnXAxisMean_NoGray'. INFO: [HLS 200-1510] Running: set_top SmoothProfileOnXAxisMean INFO: [HLS 200-1510] Running: add_files src/SmoothProfileOnXAxisMean.cpp INFO: [HLS 200-10] Adding design file 'src/SmoothProfileOnXAxisMean.cpp' to the project INFO: [HLS 200-1510] Running: add_files -tb src/SmoothProfileOnXAxisMean_test.cpp INFO: [HLS 200-10] Adding test bench file 'src/SmoothProfileOnXAxisMean_test.cpp' to the project INFO: [HLS 200-1510] Running: open_solution SmoothProfileOnXAxisMean_NoGray -flow_target vivado INFO: [HLS 200-10] Opening solution 'G:/vitis2023_project/SmoothProfileOnXAxisMean_NoGray_liangjing/SmoothProfileOnXAxisMean_NoGray/SmoothProfileOnXAxisMean_NoGray'. INFO: [SYN 201-201] Setting up clock 'default' with a period of 5ns. INFO: [HLS 200-1611] Setting target device to 'xcku060-ffva1156-2-e' INFO: [HLS 200-1505] Using flow_target 'vivado' Resolution: For help on HLS 200-1505 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2023.2%20English&url=ug1448-hls-guidance&resourceid=200-1505.html INFO: [HLS 200-1510] Running: set_part xcku060-ffva1156-2-e INFO: [HLS 200-1510] Running: create_clock -period 5 -name default INFO: [HLS 200-1510] Running: csim_design -quiet INFO: [SIM 211-2] *************** CSIM start *************** INFO: [SIM 211-4] CSIM will launch GCC as the compiler. INFO: [HLS 200-2036] Building debug C Simulation binaries Compiling ../../../../src/SmoothProfileOnXAxisMean.cpp in debug mode csim.mk:85: recipe for target 'obj/SmoothProfileOnXAxisMean.o' failed In file included from D:/vitis202302/Vitis_HLS/2023.2/include/floating_point_v7_1_bitacc_cmodel.h:150:0, from D:/vitis202302/Vitis_HLS/2023.2/include/hls_fpo.h:140, from D:/vitis202302/Vitis_HLS/2023.2/include/etc/hls_half_fpo.h:19, from D:/vitis202302/Vitis_HLS/2023.2/include/hls_half.h:26, from D:/vitis202302/Vitis_HLS/2023.2/include/etc/ap_private.h:52, from D:/vitis202302/Vitis_HLS/2023.2/include/etc/ap_common.h:666, from D:/vitis202302/Vitis_HLS/2023.2/include/ap_int.h:10, from ../../../../src/SmoothProfileOnXAxisMean.h:3, from ../../../../src/SmoothProfileOnXAxisMean.cpp:1: D:/vitis202302/Vitis_HLS/2023.2/include/gmp.h:58:0: warning: "__GMP_LIBGMP_DLL" redefined #define __GMP_LIBGMP_DLL 0 In file included from D:/vitis202302/Vitis_HLS/2023.2/include/hls_fpo.h:140:0, from D:/vitis202302/Vitis_HLS/2023.2/include/etc/hls_half_fpo.h:19, from D:/vitis202302/Vitis_HLS/2023.2/include/hls_half.h:26, from D:/vitis202302/Vitis_HLS/2023.2/include/etc/ap_private.h:52, from D:/vitis202302/Vitis_HLS/2023.2/include/etc/ap_common.h:666, from D:/vitis202302/Vitis_HLS/2023.2/include/ap_int.h:10, from ../../../../src/SmoothProfileOnXAxisMean.h:3, from ../../../../src/SmoothProfileOnXAxisMean.cpp:1: D:/vitis202302/Vitis_HLS/2023.2/include/floating_point_v7_1_bitacc_cmodel.h:142:0: note: this is the location of the previous definition #define __GMP_LIBGMP_DLL 1 ../../../../src/SmoothProfileOnXAxisMean.cpp: In function 'void SmoothProfileOnXAxisMean(hls::stream<float>&, hls::stream<float>&, ap_uint<6>, float)': ../../../../src/SmoothProfileOnXAxisMean.cpp:246:37: error: operands to ?: have different types 'int' and 'ap_int_base<6, false>::RType<32, true>::plus {aka ap_int<33>}' read_ptr = (read_ptr == 32) ? 0 : read_ptr + 1; ~~~~~~~~~~~~~~~~~^~~~~~~~~~~~~~~~~~ ../../../../src/SmoothProfileOnXAxisMean.cpp:246:37: note: and each type can be converted to the other ../../../../src/SmoothProfileOnXAxisMean.cpp:249:35: error: operands to ?: have different types 'int' and 'ap_int_base<6, false>::RType<32, true>::plus {aka ap_int<33>}' write_ptr = (write_ptr == 32) ? 0 : write_ptr + 1; ~~~~~~~~~~~~~~~~~~^~~~~~~~~~~~~~~~~~~ ../../../../src/SmoothProfileOnXAxisMean.cpp:249:35: note: and each type can be converted to the other make: *** [obj/SmoothProfileOnXAxisMean.o] Error 1 ERROR: [SIM 211-100] 'csim_design' failed: compilation error(s). INFO: [SIM 211-3] *************** CSIM finish *************** INFO: [HLS 200-111] Finished Command csim_design CPU user time: 0 seconds. CPU system time: 0 seconds. Elapsed time: 1.236 seconds; current allocated memory: 0.398 MB. 4 while executing "source G:/vitis2023_project/SmoothProfileOnXAxisMean_NoGray_liangjing/SmoothProfileOnXAxisMean_NoGray/SmoothProfileOnXAxisMean_NoGray/csim.tcl" invoked from within "hls::main G:/vitis2023_project/SmoothProfileOnXAxisMean_NoGray_liangjing/SmoothProfileOnXAxisMean_NoGray/SmoothProfileOnXAxisMean_NoGray/csim.tcl" ("uplevel" body line 1) invoked from within "uplevel 1 hls::main {*}$newargs" (procedure "hls_proc" line 16) invoked from within "hls_proc [info nameofexecutable] $argv" INFO: [HLS 200-112] Total CPU user time: 1 seconds. Total CPU system time: 1 seconds. Total elapsed time: 2.984 seconds; peak allocated memory: 199.363 MB. Finished C simulation.
07-23
INFO: [HLS 200-10] Running 'D:/vitis202302/Vitis_HLS/2023.2/bin/unwrapped/win64.o/vitis_hls.exe' INFO: [HLS 200-10] For user 'HP' on host 'desktop-qjs3vb7' (Windows NT_amd64 version 6.2) on Fri Jul 25 14:22:55 +0800 2025 INFO: [HLS 200-10] In directory 'G:/vitis2023_project/SmoothProfileOnXAxisMean_NoGray_liangjing' INFO: [HLS 200-2053] The vitis_hls executable is being deprecated. Consider using vitis-run --mode hls --tcl Sourcing Tcl script 'G:/vitis2023_project/SmoothProfileOnXAxisMean_NoGray_liangjing/SmoothProfileOnXAxisMean_NoGray/SmoothProfileOnXAxisMean_NoGray/csim.tcl' INFO: [HLS 200-1510] Running: source G:/vitis2023_project/SmoothProfileOnXAxisMean_NoGray_liangjing/SmoothProfileOnXAxisMean_NoGray/SmoothProfileOnXAxisMean_NoGray/csim.tcl INFO: [HLS 200-1510] Running: open_project SmoothProfileOnXAxisMean_NoGray INFO: [HLS 200-10] Opening project 'G:/vitis2023_project/SmoothProfileOnXAxisMean_NoGray_liangjing/SmoothProfileOnXAxisMean_NoGray'. INFO: [HLS 200-1510] Running: set_top SmoothProfileOnXAxisMeanOpt INFO: [HLS 200-1510] Running: add_files src/SmoothProfileOnXAxisMean.cpp INFO: [HLS 200-10] Adding design file 'src/SmoothProfileOnXAxisMean.cpp' to the project INFO: [HLS 200-1510] Running: add_files src/SmoothProfileOnXAxisMeanFixed.cpp INFO: [HLS 200-10] Adding design file 'src/SmoothProfileOnXAxisMeanFixed.cpp' to the project INFO: [HLS 200-1510] Running: add_files src/SmoothProfileOnXAxisMeanOpt.cpp INFO: [HLS 200-10] Adding design file 'src/SmoothProfileOnXAxisMeanOpt.cpp' to the project INFO: [HLS 200-1510] Running: add_files -tb src/SmoothProfileOnXAxisMean_test.cpp -cflags -Wno-unknown-pragmas INFO: [HLS 200-10] Adding test bench file 'src/SmoothProfileOnXAxisMean_test.cpp' to the project INFO: [HLS 200-1510] Running: open_solution SmoothProfileOnXAxisMean_NoGray -flow_target vivado INFO: [HLS 200-10] Opening solution 'G:/vitis2023_project/SmoothProfileOnXAxisMean_NoGray_liangjing/SmoothProfileOnXAxisMean_NoGray/SmoothProfileOnXAxisMean_NoGray'. INFO: [SYN 201-201] Setting up clock 'default' with a period of 5ns. INFO: [HLS 200-1611] Setting target device to 'xcku060-ffva1156-2-e' INFO: [HLS 200-1505] Using flow_target 'vivado' Resolution: For help on HLS 200-1505 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2023.2%20English&url=ug1448-hls-guidance&resourceid=200-1505.html INFO: [HLS 200-1510] Running: set_part xcku060-ffva1156-2-e INFO: [HLS 200-1510] Running: create_clock -period 5 -name default INFO: [HLS 200-1510] Running: csim_design -quiet INFO: [SIM 211-2] *************** CSIM start *************** INFO: [SIM 211-4] CSIM will launch GCC as the compiler. INFO: [HLS 200-2036] Building debug C Simulation binaries Compiling ../../../../src/SmoothProfileOnXAxisMean_test.cpp in debug mode Compiling ../../../../src/SmoothProfileOnXAxisMeanOpt.cpp in debug mode csim.mk:97: recipe for target 'obj/SmoothProfileOnXAxisMeanOpt.o' failed In file included from D:/vitis202302/Vitis_HLS/2023.2/include/floating_point_v7_1_bitacc_cmodel.h:150:0, from D:/vitis202302/Vitis_HLS/2023.2/include/hls_fpo.h:140, from D:/vitis202302/Vitis_HLS/2023.2/include/etc/hls_half_fpo.h:19, from D:/vitis202302/Vitis_HLS/2023.2/include/hls_half.h:26, from D:/vitis202302/Vitis_HLS/2023.2/include/etc/ap_private.h:52, from D:/vitis202302/Vitis_HLS/2023.2/include/etc/ap_common.h:666, from D:/vitis202302/Vitis_HLS/2023.2/include/ap_int.h:10, from ../../../../src/SmoothProfileOnXAxisMean.h:3, from ../../../../src/SmoothProfileOnXAxisMean_test.cpp:1: D:/vitis202302/Vitis_HLS/2023.2/include/gmp.h:58:0: warning: "__GMP_LIBGMP_DLL" redefined #define __GMP_LIBGMP_DLL 0 In file included from D:/vitis202302/Vitis_HLS/2023.2/include/hls_fpo.h:140:0, from D:/vitis202302/Vitis_HLS/2023.2/include/etc/hls_half_fpo.h:19, from D:/vitis202302/Vitis_HLS/2023.2/include/hls_half.h:26, from D:/vitis202302/Vitis_HLS/2023.2/include/etc/ap_private.h:52, from D:/vitis202302/Vitis_HLS/2023.2/include/etc/ap_common.h:666, from D:/vitis202302/Vitis_HLS/2023.2/include/ap_int.h:10, from ../../../../src/SmoothProfileOnXAxisMean.h:3, from ../../../../src/SmoothProfileOnXAxisMean_test.cpp:1: D:/vitis202302/Vitis_HLS/2023.2/include/floating_point_v7_1_bitacc_cmodel.h:142:0: note: this is the location of the previous definition #define __GMP_LIBGMP_DLL 1 In file included from D:/vitis202302/Vitis_HLS/2023.2/include/floating_point_v7_1_bitacc_cmodel.h:150:0, from D:/vitis202302/Vitis_HLS/2023.2/include/hls_fpo.h:140, from D:/vitis202302/Vitis_HLS/2023.2/include/etc/hls_half_fpo.h:19, from D:/vitis202302/Vitis_HLS/2023.2/include/hls_half.h:26, from D:/vitis202302/Vitis_HLS/2023.2/include/etc/ap_private.h:52, from D:/vitis202302/Vitis_HLS/2023.2/include/etc/ap_common.h:666, from D:/vitis202302/Vitis_HLS/2023.2/include/ap_int.h:10, from ../../../../src/SmoothProfileOnXAxisMean.h:3, from ../../../../src/SmoothProfileOnXAxisMeanOpt.cpp:1: D:/vitis202302/Vitis_HLS/2023.2/include/gmp.h:58:0: warning: "__GMP_LIBGMP_DLL" redefined #define __GMP_LIBGMP_DLL 0 In file included from D:/vitis202302/Vitis_HLS/2023.2/include/hls_fpo.h:140:0, from D:/vitis202302/Vitis_HLS/2023.2/include/etc/hls_half_fpo.h:19, from D:/vitis202302/Vitis_HLS/2023.2/include/hls_half.h:26, from D:/vitis202302/Vitis_HLS/2023.2/include/etc/ap_private.h:52, from D:/vitis202302/Vitis_HLS/2023.2/include/etc/ap_common.h:666, from D:/vitis202302/Vitis_HLS/2023.2/include/ap_int.h:10, from ../../../../src/SmoothProfileOnXAxisMean.h:3, from ../../../../src/SmoothProfileOnXAxisMeanOpt.cpp:1: D:/vitis202302/Vitis_HLS/2023.2/include/floating_point_v7_1_bitacc_cmodel.h:142:0: note: this is the location of the previous definition #define __GMP_LIBGMP_DLL 1 ../../../../src/SmoothProfileOnXAxisMeanOpt.cpp: In function 'void SmoothProfileOnXAxisMeanOpt(hls::stream<float>&, hls::stream<float>&, ap_uint<6>, float)': ../../../../src/SmoothProfileOnXAxisMeanOpt.cpp:41:28: error: 'i' was not declared in this scope bool data_available = (i < 3200); ^ ../../../../src/SmoothProfileOnXAxisMeanOpt.cpp:48:9: error: continue statement not within a loop continue; ^~~~~~~~ ../../../../src/SmoothProfileOnXAxisMeanOpt.cpp:52:9: error: continue statement not within a loop continue; ^~~~~~~~ ../../../../src/SmoothProfileOnXAxisMeanOpt.cpp:73:62: error: ambiguous overload for 'operator*' (operand types are 'ap_fixed_base<18, 5, true, (ap_q_mode)5u, (ap_o_mode)3u, 0>::RType<24, 11, true>::minus {aka ap_fixed<25, 12, (ap_q_mode)5u, (ap_o_mode)3u, 0>}' and 'float') fixed_t compensation = (sum - avg * valid_count) * 0.01f; ~~~~~~~~~~~~~~~~~~~~~~~~~~^~~~~~~ ../../../../src/SmoothProfileOnXAxisMeanOpt.cpp:73:62: note: candidate: operator*(long double, float) <built-in> ../../../../src/SmoothProfileOnXAxisMeanOpt.cpp:73:62: note: candidate: operator*(double, float) <built-in> ../../../../src/SmoothProfileOnXAxisMeanOpt.cpp:73:62: note: candidate: operator*(float, float) <built-in> ../../../../src/SmoothProfileOnXAxisMeanOpt.cpp:73:62: note: candidate: operator*(int, float) <built-in> ../../../../src/SmoothProfileOnXAxisMeanOpt.cpp:73:62: note: candidate: operator*(unsigned int, float) <built-in> ../../../../src/SmoothProfileOnXAxisMeanOpt.cpp:73:62: note: candidate: operator*(long int, float) <built-in> ../../../../src/SmoothProfileOnXAxisMeanOpt.cpp:73:62: note: candidate: operator*(long unsigned int, float) <built-in> ../../../../src/SmoothProfileOnXAxisMeanOpt.cpp:73:62: note: candidate: operator*(ap_ulong {aka long long unsigned int}, float) <built-in> ../../../../src/SmoothProfileOnXAxisMeanOpt.cpp:73:62: note: candidate: operator*(ap_slong {aka long long int}, float) <built-in> In file included from D:/vitis202302/Vitis_HLS/2023.2/include/ap_fixed.h:10:0, from D:/vitis202302/Vitis_HLS/2023.2/include/ap_int.h:360, from ../../../../src/SmoothProfileOnXAxisMean.h:3, from ../../../../src/SmoothProfileOnXAxisMeanOpt.cpp:1: D:/vitis202302/Vitis_HLS/2023.2/include/etc/ap_fixed_base.h:2293:3: note: candidate: typename ap_fixed_base<_AP_W, _AP_I, _AP_S>::RType<_AP_SIZE_ap_slong, _AP_SIZE_ap_slong, false>::mult operator*(const ap_fixed_base<_AP_W, _AP_I, _AP_S, _AP_Q, _AP_O, _AP_N>&, ap_ulong) [with int _AP_W = 25; int _AP_I = 12; bool _AP_S = true; ap_q_mode _AP_Q = (ap_q_mode)5u; ap_o_mode _AP_O = (ap_o_mode)3u; int _AP_N = 0; typename ap_fixed_base<_AP_W, _AP_I, _AP_S>::RType<_AP_SIZE_ap_slong, _AP_SIZE_ap_slong, false>::mult = ap_fixed<89, 76, (ap_q_mode)5u, (ap_o_mode)3u, 0>; ap_ulong = long long unsigned int] operator BIN_OP( \ ^ D:/vitis202302/Vitis_HLS/2023.2/include/etc/ap_fixed_base.h:2347:3: note: in expansion of macro 'AF_BIN_OP_WITH_INT' AF_BIN_OP_WITH_INT(*, C_TYPE, (BITS), (SIGN), mult) \ ^~~~~~~~~~~~~~~~~~ D:/vitis202302/Vitis_HLS/2023.2/include/etc/ap_fixed_base.h:2383:1: note: in expansion of macro 'ALL_AF_OP_WITH_INT' ALL_AF_OP_WITH_INT(ap_ulong, _AP_SIZE_ap_slong, false) ^~~~~~~~~~~~~~~~~~ D:/vitis202302/Vitis_HLS/2023.2/include/etc/ap_fixed_base.h:2293:3: note: candidate: typename ap_fixed_base<_AP_W, _AP_I, _AP_S>::RType<_AP_SIZE_ap_slong, _AP_SIZE_ap_slong, true>::mult operator*(const ap_fixed_base<_AP_W, _AP_I, _AP_S, _AP_Q, _AP_O, _AP_N>&, ap_slong) [with int _AP_W = 25; int _AP_I = 12; bool _AP_S = true; ap_q_mode _AP_Q = (ap_q_mode)5u; ap_o_mode _AP_O = (ap_o_mode)3u; int _AP_N = 0; typename ap_fixed_base<_AP_W, _AP_I, _AP_S>::RType<_AP_SIZE_ap_slong, _AP_SIZE_ap_slong, true>::mult = ap_fixed<89, 76, (ap_q_mode)5u, (ap_o_mode)3u, 0>; ap_slong = long long int] operator BIN_OP( \ ^ D:/vitis202302/Vitis_HLS/2023.2/include/etc/ap_fixed_base.h:2347:3: note: in expansion of macro 'AF_BIN_OP_WITH_INT' AF_BIN_OP_WITH_INT(*, C_TYPE, (BITS), (SIGN), mult) \ ^~~~~~~~~~~~~~~~~~ D:/vitis202302/Vitis_HLS/2023.2/include/etc/ap_fixed_base.h:2382:1: note: in expansion of macro 'ALL_AF_OP_WITH_INT' ALL_AF_OP_WITH_INT(ap_slong, _AP_SIZE_ap_slong, true) ^~~~~~~~~~~~~~~~~~ D:/vitis202302/Vitis_HLS/2023.2/include/etc/ap_fixed_base.h:2293:3: note: candidate: typename ap_fixed_base<_AP_W, _AP_I, _AP_S>::RType<_AP_SIZE_long, _AP_SIZE_long, false>::mult operator*(const ap_fixed_base<_AP_W, _AP_I, _AP_S, _AP_Q, _AP_O, _AP_N>&, long unsigned int) [with int _AP_W = 25; int _AP_I = 12; bool _AP_S = true; ap_q_mode _AP_Q = (ap_q_mode)5u; ap_o_mode _AP_O = (ap_o_mode)3u; int _AP_N = 0; typename ap_fixed_base<_AP_W, _AP_I, _AP_S>::RType<_AP_SIZE_long, _AP_SIZE_long, false>::mult = ap_fixed<57, 44, (ap_q_mode)5u, (ap_o_mode)3u, 0>] operator BIN_OP( \ ^ D:/vitis202302/Vitis_HLS/2023.2/include/etc/ap_fixed_base.h:2347:3: note: in expansion of macro 'AF_BIN_OP_WITH_INT' AF_BIN_OP_WITH_INT(*, C_TYPE, (BITS), (SIGN), mult) \ ^~~~~~~~~~~~~~~~~~ D:/vitis202302/Vitis_HLS/2023.2/include/etc/ap_fixed_base.h:2381:1: note: in expansion of macro 'ALL_AF_OP_WITH_INT' ALL_AF_OP_WITH_INT(unsigned long, _AP_SIZE_long, false) ^~~~~~~~~~~~~~~~~~ D:/vitis202302/Vitis_HLS/2023.2/include/etc/ap_fixed_base.h:2293:3: note: candidate: typename ap_fixed_base<_AP_W, _AP_I, _AP_S>::RType<_AP_SIZE_long, _AP_SIZE_long, true>::mult operator*(const ap_fixed_base<_AP_W, _AP_I, _AP_S, _AP_Q, _AP_O, _AP_N>&, long int) [with int _AP_W = 25; int _AP_I = 12; bool _AP_S = true; ap_q_mode _AP_Q = (ap_q_mode)5u; ap_o_mode _AP_O = (ap_o_mode)3u; int _AP_N = 0; typename ap_fixed_base<_AP_W, _AP_I, _AP_S>::RType<_AP_SIZE_long, _AP_SIZE_long, true>::mult = ap_fixed<57, 44, (ap_q_mode)5u, (ap_o_mode)3u, 0>] operator BIN_OP( \ ^ D:/vitis202302/Vitis_HLS/2023.2/include/etc/ap_fixed_base.h:2347:3: note: in expansion of macro 'AF_BIN_OP_WITH_INT' AF_BIN_OP_WITH_INT(*, C_TYPE, (BITS), (SIGN), mult) \ ^~~~~~~~~~~~~~~~~~ D:/vitis202302/Vitis_HLS/2023.2/include/etc/ap_fixed_base.h:2380:1: note: in expansion of macro 'ALL_AF_OP_WITH_INT' ALL_AF_OP_WITH_INT(long, _AP_SIZE_long, true) ^~~~~~~~~~~~~~~~~~ D:/vitis202302/Vitis_HLS/2023.2/include/etc/ap_fixed_base.h:2293:3: note: candidate: typename ap_fixed_base<_AP_W, _AP_I, _AP_S>::RType<_AP_SIZE_int, _AP_SIZE_int, false>::mult operator*(const ap_fixed_base<_AP_W, _AP_I, _AP_S, _AP_Q, _AP_O, _AP_N>&, unsigned int) [with int _AP_W = 25; int _AP_I = 12; bool _AP_S = true; ap_q_mode _AP_Q = (ap_q_mode)5u; ap_o_mode _AP_O = (ap_o_mode)3u; int _AP_N = 0; typename ap_fixed_base<_AP_W, _AP_I, _AP_S>::RType<_AP_SIZE_int, _AP_SIZE_int, false>::mult = ap_fixed<57, 44, (ap_q_mode)5u, (ap_o_mode)3u, 0>] operator BIN_OP( \ ^ D:/vitis202302/Vitis_HLS/2023.2/include/etc/ap_fixed_base.h:2347:3: note: in expansion of macro 'AF_BIN_OP_WITH_INT' AF_BIN_OP_WITH_INT(*, C_TYPE, (BITS), (SIGN), mult) \ ^~~~~~~~~~~~~~~~~~ D:/vitis202302/Vitis_HLS/2023.2/include/etc/ap_fixed_base.h:2379:1: note: in expansion of macro 'ALL_AF_OP_WITH_INT' ALL_AF_OP_WITH_INT(unsigned int, _AP_SIZE_int, false) ^~~~~~~~~~~~~~~~~~ D:/vitis202302/Vitis_HLS/2023.2/include/etc/ap_fixed_base.h:2293:3: note: candidate: typename ap_fixed_base<_AP_W, _AP_I, _AP_S>::RType<_AP_SIZE_int, _AP_SIZE_int, true>::mult operator*(const ap_fixed_base<_AP_W, _AP_I, _AP_S, _AP_Q, _AP_O, _AP_N>&, int) [with int _AP_W = 25; int _AP_I = 12; bool _AP_S = true; ap_q_mode _AP_Q = (ap_q_mode)5u; ap_o_mode _AP_O = (ap_o_mode)3u; int _AP_N = 0; typename ap_fixed_base<_AP_W, _AP_I, _AP_S>::RType<_AP_SIZE_int, _AP_SIZE_int, true>::mult = ap_fixed<57, 44, (ap_q_mode)5u, (ap_o_mode)3u, 0>] operator BIN_OP( \ ^ D:/vitis202302/Vitis_HLS/2023.2/include/etc/ap_fixed_base.h:2347:3: note: in expansion of macro 'AF_BIN_OP_WITH_INT' AF_BIN_OP_WITH_INT(*, C_TYPE, (BITS), (SIGN), mult) \ ^~~~~~~~~~~~~~~~~~ D:/vitis202302/Vitis_HLS/2023.2/include/etc/ap_fixed_base.h:2378:1: note: in expansion of macro 'ALL_AF_OP_WITH_INT' ALL_AF_OP_WITH_INT(int, _AP_SIZE_int, true) ^~~~~~~~~~~~~~~~~~ D:/vitis202302/Vitis_HLS/2023.2/include/etc/ap_fixed_base.h:2293:3: note: candidate: typename ap_fixed_base<_AP_W, _AP_I, _AP_S>::RType<_AP_SIZE_short, _AP_SIZE_short, false>::mult operator*(const ap_fixed_base<_AP_W, _AP_I, _AP_S, _AP_Q, _AP_O, _AP_N>&, short unsigned int) [with int _AP_W = 25; int _AP_I = 12; bool _AP_S = true; ap_q_mode _AP_Q = (ap_q_mode)5u; ap_o_mode _AP_O = (ap_o_mode)3u; int _AP_N = 0; typename ap_fixed_base<_AP_W, _AP_I, _AP_S>::RType<_AP_SIZE_short, _AP_SIZE_short, false>::mult = ap_fixed<41, 28, (ap_q_mode)5u, (ap_o_mode)3u, 0>] operator BIN_OP( \ ^ D:/vitis202302/Vitis_HLS/2023.2/include/etc/ap_fixed_base.h:2347:3: note: in expansion of macro 'AF_BIN_OP_WITH_INT' AF_BIN_OP_WITH_INT(*, C_TYPE, (BITS), (SIGN), mult) \ ^~~~~~~~~~~~~~~~~~ D:/vitis202302/Vitis_HLS/2023.2/include/etc/ap_fixed_base.h:2377:1: note: in expansion of macro 'ALL_AF_OP_WITH_INT' ALL_AF_OP_WITH_INT(unsigned short, _AP_SIZE_short, false) ^~~~~~~~~~~~~~~~~~ D:/vitis202302/Vitis_HLS/2023.2/include/etc/ap_fixed_base.h:2293:3: note: candidate: typename ap_fixed_base<_AP_W, _AP_I, _AP_S>::RType<_AP_SIZE_short, _AP_SIZE_short, true>::mult operator*(const ap_fixed_base<_AP_W, _AP_I, _AP_S, _AP_Q, _AP_O, _AP_N>&, short int) [with int _AP_W = 25; int _AP_I = 12; bool _AP_S = true; ap_q_mode _AP_Q = (ap_q_mode)5u; ap_o_mode _AP_O = (ap_o_mode)3u; int _AP_N = 0; typename ap_fixed_base<_AP_W, _AP_I, _AP_S>::RType<_AP_SIZE_short, _AP_SIZE_short, true>::mult = ap_fixed<41, 28, (ap_q_mode)5u, (ap_o_mode)3u, 0>] operator BIN_OP( \ ^ D:/vitis202302/Vitis_HLS/2023.2/include/etc/ap_fixed_base.h:2347:3: note: in expansion of macro 'AF_BIN_OP_WITH_INT' AF_BIN_OP_WITH_INT(*, C_TYPE, (BITS), (SIGN), mult) \ ^~~~~~~~~~~~~~~~~~ D:/vitis202302/Vitis_HLS/2023.2/include/etc/ap_fixed_base.h:2376:1: note: in expansion of macro 'ALL_AF_OP_WITH_INT' ALL_AF_OP_WITH_INT(short, _AP_SIZE_short, true) ^~~~~~~~~~~~~~~~~~ D:/vitis202302/Vitis_HLS/2023.2/include/etc/ap_fixed_base.h:2293:3: note: candidate: typename ap_fixed_base<_AP_W, _AP_I, _AP_S>::RType<8, 8, false>::mult operator*(const ap_fixed_base<_AP_W, _AP_I, _AP_S, _AP_Q, _AP_O, _AP_N>&, unsigned char) [with int _AP_W = 25; int _AP_I = 12; bool _AP_S = true; ap_q_mode _AP_Q = (ap_q_mode)5u; ap_o_mode _AP_O = (ap_o_mode)3u; int _AP_N = 0; typename ap_fixed_base<_AP_W, _AP_I, _AP_S>::RType<8, 8, false>::mult = ap_fixed<33, 20, (ap_q_mode)5u, (ap_o_mode)3u, 0>] operator BIN_OP( \ ^ D:/vitis202302/Vitis_HLS/2023.2/include/etc/ap_fixed_base.h:2347:3: note: in expansion of macro 'AF_BIN_OP_WITH_INT' AF_BIN_OP_WITH_INT(*, C_TYPE, (BITS), (SIGN), mult) \ ^~~~~~~~~~~~~~~~~~ D:/vitis202302/Vitis_HLS/2023.2/include/etc/ap_fixed_base.h:2375:1: note: in expansion of macro 'ALL_AF_OP_WITH_INT' ALL_AF_OP_WITH_INT(unsigned char, 8, false) ^~~~~~~~~~~~~~~~~~ D:/vitis202302/Vitis_HLS/2023.2/include/etc/ap_fixed_base.h:2293:3: note: candidate: typename ap_fixed_base<_AP_W, _AP_I, _AP_S>::RType<8, 8, true>::mult operator*(const ap_fixed_base<_AP_W, _AP_I, _AP_S, _AP_Q, _AP_O, _AP_N>&, signed char) [with int _AP_W = 25; int _AP_I = 12; bool _AP_S = true; ap_q_mode _AP_Q = (ap_q_mode)5u; ap_o_mode _AP_O = (ap_o_mode)3u; int _AP_N = 0; typename ap_fixed_base<_AP_W, _AP_I, _AP_S>::RType<8, 8, true>::mult = ap_fixed<33, 20, (ap_q_mode)5u, (ap_o_mode)3u, 0>] operator BIN_OP( \ ^ D:/vitis202302/Vitis_HLS/2023.2/include/etc/ap_fixed_base.h:2347:3: note: in expansion of macro 'AF_BIN_OP_WITH_INT' AF_BIN_OP_WITH_INT(*, C_TYPE, (BITS), (SIGN), mult) \ ^~~~~~~~~~~~~~~~~~ D:/vitis202302/Vitis_HLS/2023.2/include/etc/ap_fixed_base.h:2374:1: note: in expansion of macro 'ALL_AF_OP_WITH_INT' ALL_AF_OP_WITH_INT(signed char, 8, true) ^~~~~~~~~~~~~~~~~~ D:/vitis202302/Vitis_HLS/2023.2/include/etc/ap_fixed_base.h:2293:3: note: candidate: typename ap_fixed_base<_AP_W, _AP_I, _AP_S>::RType<8, 8, CHAR_IS_SIGNED>::mult operator*(const ap_fixed_base<_AP_W, _AP_I, _AP_S, _AP_Q, _AP_O, _AP_N>&, char) [with int _AP_W = 25; int _AP_I = 12; bool _AP_S = true; ap_q_mode _AP_Q = (ap_q_mode)5u; ap_o_mode _AP_O = (ap_o_mode)3u; int _AP_N = 0; typename ap_fixed_base<_AP_W, _AP_I, _AP_S>::RType<8, 8, CHAR_IS_SIGNED>::mult = ap_fixed<33, 20, (ap_q_mode)5u, (ap_o_mode)3u, 0>] operator BIN_OP( \ ^ D:/vitis202302/Vitis_HLS/2023.2/include/etc/ap_fixed_base.h:2347:3: note: in expansion of macro 'AF_BIN_OP_WITH_INT' AF_BIN_OP_WITH_INT(*, C_TYPE, (BITS), (SIGN), mult) \ ^~~~~~~~~~~~~~~~~~ D:/vitis202302/Vitis_HLS/2023.2/include/etc/ap_fixed_base.h:2373:1: note: in expansion of macro 'ALL_AF_OP_WITH_INT' ALL_AF_OP_WITH_INT(char, 8, CHAR_IS_SIGNED) ^~~~~~~~~~~~~~~~~~ D:/vitis202302/Vitis_HLS/2023.2/include/etc/ap_fixed_base.h:2293:3: note: candidate: typename ap_fixed_base<_AP_W, _AP_I, _AP_S>::RType<1, 1, false>::mult operator*(const ap_fixed_base<_AP_W, _AP_I, _AP_S, _AP_Q, _AP_O, _AP_N>&, bool) [with int _AP_W = 25; int _AP_I = 12; bool _AP_S = true; ap_q_mode _AP_Q = (ap_q_mode)5u; ap_o_mode _AP_O = (ap_o_mode)3u; int _AP_N = 0; typename ap_fixed_base<_AP_W, _AP_I, _AP_S>::RType<1, 1, false>::mult = ap_fixed<26, 13, (ap_q_mode)5u, (ap_o_mode)3u, 0>] operator BIN_OP( \ ^ D:/vitis202302/Vitis_HLS/2023.2/include/etc/ap_fixed_base.h:2347:3: note: in expansion of macro 'AF_BIN_OP_WITH_INT' AF_BIN_OP_WITH_INT(*, C_TYPE, (BITS), (SIGN), mult) \ ^~~~~~~~~~~~~~~~~~ D:/vitis202302/Vitis_HLS/2023.2/include/etc/ap_fixed_base.h:2372:1: note: in expansion of macro 'ALL_AF_OP_WITH_INT' ALL_AF_OP_WITH_INT(bool, 1, false) ^~~~~~~~~~~~~~~~~~ make: *** [obj/SmoothProfileOnXAxisMeanOpt.o] Error 1 ERROR: [SIM 211-100] 'csim_design' failed: compilation error(s). INFO: [SIM 211-3] *************** CSIM finish *************** INFO: [HLS 200-111] Finished Command csim_design CPU user time: 0 seconds. CPU system time: 0 seconds. Elapsed time: 3.165 seconds; current allocated memory: 0.410 MB. 4 while executing "source G:/vitis2023_project/SmoothProfileOnXAxisMean_NoGray_liangjing/SmoothProfileOnXAxisMean_NoGray/SmoothProfileOnXAxisMean_NoGray/csim.tcl" invoked from within "hls::main G:/vitis2023_project/SmoothProfileOnXAxisMean_NoGray_liangjing/SmoothProfileOnXAxisMean_NoGray/SmoothProfileOnXAxisMean_NoGray/csim.tcl" ("uplevel" body line 1) invoked from within "uplevel 1 hls::main {*}$newargs" (procedure "hls_proc" line 16) invoked from within "hls_proc [info nameofexecutable] $argv" INFO: [HLS 200-112] Total CPU user time: 1 seconds. Total CPU system time: 1 seconds. Total elapsed time: 5.2 seconds; peak allocated memory: 199.391 MB. Finished C simulation.
最新发布
07-26
评论
添加红包

请填写红包祝福语或标题

红包个数最小为10个

红包金额最低5元

当前余额3.43前往充值 >
需支付:10.00
成就一亿技术人!
领取后你会自动成为博主和红包主的粉丝 规则
hope_wisdom
发出的红包
实付
使用余额支付
点击重新获取
扫码支付
钱包余额 0

抵扣说明:

1.余额是钱包充值的虚拟货币,按照1:1的比例进行支付金额的抵扣。
2.余额无法直接购买下载,可以购买VIP、付费专栏及课程。

余额充值