RISC-V International’s new VP of Technology Tom Gall reflected on his first RISC-V Summit North America in his new role, highlighting a packed program of keynotes, panels, and expert talks. From early RISC history to bold visions for open standard computing, Tom shared what themes stood out at the show, including: - Space is leading the incumbent markets, and RISC-V is poised to own it - Standardization and choice can successfully coexist - RISC-V's next big AI opportunity lies at the edge Read his top 7 takeaways from #RISCVSummit: https://hubs.la/Q03V-Y8K0
RISC-V International
Herstellung von Computerhardware
The non-profit home of the open standard RISC-V ISA, related specifications, and stakeholder community.
Info
RISC-V International is the non-profit home of the open standard RISC-V Instruction Set Architecture (ISA), related specifications, and stakeholder community. With global membership across 70 different countries, over 4,200 members are contributing and collaborating to define RISC-V open specifications as well as convene and govern related technical, industry, domain, and special interest groups. RISC-V combines a modular technical approach with an open, royalty-free license model -- meaning that anyone, anywhere can leverage the IP contributed and produced by RISC-V. RISC-V enables the community to share technical investment, contribute to the strategic future, create more rapidly, enjoy unprecedented design freedom, and substantially reduce the cost of innovation.
- Website
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http://www.riscv.org
Externer Link zu RISC-V International
- Branche
- Herstellung von Computerhardware
- Größe
- 2–10 Beschäftigte
- Hauptsitz
- Zurich
- Art
- Nonprofit
- Gegründet
- 2015
Orte
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Primär
Wegbeschreibung
Zurich, CH
Beschäftigte von RISC-V International
Updates
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At #RISCVSummitEurope 2025, Embecosm demonstrated how the #oneAPI Construction Kit helps bring the open oneAPI ecosystem to new hardware. Their project explored accelerating #PyTorch on RISC-V, trying over a thousand cores in emulation and even on an #FPGA. Discover how open standards like C++ and SYCL are enabling high-performance AI on #RISCV: 👉https://lnkd.in/dCuCewHH #RISCVFeaturedWork by: Alastair Murray ________________________________________________________________ #AI #OpenStandard #DesignTools #Embedded #Cloud #Software
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Why does openness matter for AI at the edge? Edge AI is becoming central to industries that demand autonomy, reliability, and real-time intelligence. It includes systems performing AI inferencing directly where data is created, from industrial gateways monitoring production lines to connected vehicles on the road and autonomous robots on warehouse floors. But performance alone isn’t enough. Success at the edge requires openness. Open architectures, frameworks, and standards like RISC-V enable devices and ecosystems to work together, avoiding vendor lock-in and accelerating innovation. Learn more from Semiconductor Engineering: https://hubs.la/Q03V-XSS0
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RISC-V International hat dies direkt geteilt
Yesterday, in the CadenceCONNECT Club Formal in the UK, our CEO Ashish Darbari showcased a groundbreaking technology CoreProve for end-to-end #formalverification sign-off. Designed by Axiomise experts, CoreProve is an advanced abstraction engine that establishes proof convergence for complex end-to-end checks in formal property checking tools ensuring you don’t miss a bug and prove bug absence. Initial testing on a wide variety of designs reveals amazing acceleration in proof times and is turning intractable problems provable in seconds. In case you couldn’t make it yesterday to the event watch the teaser. REGISTER YOUR INTEREST AT: https://lnkd.in/epg-8Sq9
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Cyber Week is on! Boost your #RISCV skills with up to 65% off the RISC-V Fundamentals Course and RVFA Certification. This is the perfect opportunity to learn, grow, and get RISC-V certified. 📅 Promo runs December 1–9. This is our biggest sale of the year, don’t miss out! Save Now: https://hubs.la/Q03VXspQ0 #CyberWeek #RISCVcertified
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RISC-V International was recently approved as a JTC 1 PAS submitter, strengthening the organization’s collaborative network and enabling it to collaborate with peers who prioritize shared learning and problem-solving. RISC-V International will engage with other PAS submitters, JTC1 committees, and working groups, from AI to cybersecurity and beyond. RISC-V International looks forward to continuing to strengthen global trust, foster interoperability, and cement RISC-V’s role as the foundation for the future of open computing. Learn more: https://hubs.la/Q03VQ3DM0
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RISC-V International hat dies direkt geteilt
Interested in join us in our RISC-V booth at embedded world 2026? We 4 kiosk spots left and 2 Hall 5 panel slots available. Check out the prospectus at https://lnkd.in/d97ae9xf and email [email protected] before everything is sold out.
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Space and aerospace systems need secure, high-performance processing to power emerging AI workloads, from fully autonomous operations to onboard science computing. These missions demand exceptional reliability, fault tolerance in harsh environments, functional safety, and energy efficiency. RISC-V can be precisely tailored to meet these needs. As the only open, industry-standard ISA that scales across the full range of mission requirements, RISC-V delivers unique customization and a resilient, diverse supply-chain ecosystem. 🪐 Explore how RISC-V is reaching new orbits in space computing: https://hubs.la/Q03VHYtn0 #RISCVInSpace #RISCVEverywhere
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What was your biggest takeaway from #RISCV Summit North America 2025? For our new VP of Technology Tom Gall, 7 things stood out: 1. Patterson’s Radical #RISC Wager Defied the Entire Playbook 2. #Space Is Leading the Incumbents, and RISC-V Is Poised to Own It 3. RISC-V’s Next Big #AIOpportunity Lies at the Edge 4. CUDA Will Turbocharge RISC-V #Supercomputing/ #HPC 5. You Can Access a RISC-V #FPGA Right Now, via #AWS 6. Upstreaming Remains A Heated Issue 7. Standardization Can Coexist With Choice 7 is an odd number. Will you help us get it to 10? What made you stop, think, reconsider or simply marvel during the Summit? Let us know in the comments below or via email (james @ riscv.org)!
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💡Ever wondered how Virtual Prototypes can transform hardware design for AI at the edge? Our latest #RISCVFeaturedWork dives into how researchers use virtual platforms to uncover hardware optimizations that traditional methods often miss. By applying MLPerf Tiny benchmarks, they reveal smarter, more efficient HW configurations for neural network inference. Explore the findings and get inspired by what’s possible with Virtual Prototypes! https://lnkd.in/dqrcJigH Authors: Jan Zielasko & Rolf Drechsler #RISCV #AI #EdgeComputing #MLPerf #VirtualPrototypes
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