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https://blog.csdn.net/weixin_45791458/category_12828932.html?spm=1001.2014.3001.5482本文是对VC Spyglass CDC Hands-on Training中第一个实验的翻译（有删改），Lab文件可以从以下链接获取。
实验概述
本次实验将帮助用户熟悉VC SpyGlass CDC的使用模式及其功能，实验内容包括以下方面：
- 调试时钟设置问题并即时应用CDC约束
- 识别未同步的跨时钟域并通过CDC约束进行修复
实验一、CDC设置
本实验旨在帮助用户掌握进行CDC验证所需的设计与约束配置流程，并初步熟悉批处理模式与用户图形界面(GUI)的基本操作。实验中将指导用户识别并验证时钟和复位信号的设置，同时确认控制信号配置的正确性。
通过本实验，用户将学习以下内容：
-
如何进行设计环境的基本设置
-
如何从候选时钟/复位信号中识别出真实的时钟/复位
-
如何验证时钟和复位信号的设置信息
-
如何确认控制信号的设置是否正确
简单说明
本实验假设用户已经完全迁移到VC Spyglass，使用VC Spyglass使用模式(VCUM)而不是向后兼容的Spyglass使用模式(SGUM)，关于SGUM的更多介绍，可以参考下面的博客。
作为第一步，用户需要创建一个名为vc_cdc.tcl的文件（该文件已提供），并通过set_app_var命令打开CDC分析功能，然后可以使用analyze/elaborate命令读取RTL文件，使用read_sdc命令读取约束文件。下面是一个示例TCL文件，展示了上述操作的写法。
#### 设置应用变量
set_app_var enable_cdc true
#### 读取设计文件
analyze -format verilog {-f <RTL_Filelist>} -vcs {-sv=2005 }
elaborate <Top_Module>
#### 读取用户提供的SDC约束文件
read_sdc <SDC_File>运行VC Spyglass
1、进入实验一的目录。
% cd VC_SpyGlass_Structural_CDC_Lab/Lab1_setup/2、可以选择以批处理方式(Batch)或图形用户界面(GUI)运行VC Spyglass。本实验将使用批处理方式运行，然后在运行完成后再启动图形用户界面。
% vc_static_shell -f vc_cdc.tcl
如果想以图形用户界面VC Spyglass，使用-verdi选项即可。
% vc_static_shell -f vc_cdc.tcl -verdiVC Spyglass的运行结果如下所示，注意到其中存在Error。
vc_static_shell> #### Setting app var
set_app_var enable_cdc true
true
#set_blackbox -design BBOX_CLOCK
#### Design read
analyze -format verilog { -f training.f } -vcs { -sv=2005 }
1
elaborate training
[Warning] COM_OPT009: 'search_path' has not been set.
[Warning] COM_OPT010: 'link_library' has not been set.
Doing common elaboration
Final timescale is '1ps/1ps'
Warning-[TFIPC] Too few instance port connections
../RTL/aslp128x8secwr.v, 92
aslp128x8secwr, "aslp128x8secwr_count_rd u_aslp128x8secwr_count_rd( .clock (rd_clock), .reset_n (rd_reset_n), .reset (rd_reset), .request (rd_ready), .valid (rd_valid), .address (rd_address), .count (rd_count), .empty (rd_empty), .reset_in (wr_rd_reset), .reset_out (rd_wr_reset), .gray_in (wr_rd_gray), .gray_out (rd_wr_gray));"
The above instance has fewer port connections than the module definition.
Please use '+lint=TFIPC-L' to print out detailed information of unconnected
ports.
Warning-[TFIPC] Too few instance port connections
../RTL/training.v, 29
training, "rule_Clock_info03a u_CI03a( .clk (Clock_info03a_clk), .data_in (inputA), .reset_n (reset_n), .data_out (rule_Clock_info03a_out));"
The above instance has fewer port connections than the module definition.
Please use '+lint=TFIPC-L' to print out detailed information of unconnected
ports.
Warning-[TFIPC] Too few instance port connections
../RTL/training.v, 31
training, "rule_Clock_info05 u_CI05( .clkA (clkA), .clkB (clkB), .sel (Clock_info05_sel), .inputA (inputA), .reset (reset_u), .data_out (rule_Clock_info05_out));"
The above instance has fewer port connections than the module definition.
Please use '+lint=TFIPC-L' to print out detailed information of unconnected
ports.
Warning-[TFIPC] Too few instance port connections
../RTL/training.v, 33
training, "rule_Ac_sync01 u_ACS01( .clkS (clkA), .clkD (clkB), .d (inputA), .reset_n (reset_n));"
The above instance has fewer port connections than the module definition.
Please use '+lint=TFIPC-L' to print out detailed information of unconnected
ports.
Warning-[TFIPC] Too few instance port connections
../RTL/training.v, 38
training, "aslp128x8secwr u_aslp128x8secwr( .wr_clock (clkA), .rd_clock (clkB));"
The above instance has fewer port connections than the module definition.
Please use '+lint=TFIPC-L' to print out detailed information of unconnected
ports.
Warning-[TFIPC] Too few instance port connections
../RTL/training.v, 42
training, "CSCR u_CSCR( .clkS (clkE), .clkD (clkF), .d (inputA), .reset_n (reset_n));"
The above instance has fewer port connections than the module definition.
Please use '+lint=TFIPC-L' to print out detailed information of unconnected
ports.
Warning-[PCWM-W] Port connection width mismatch
../RTL/training.v, 33
"rule_Ac_sync01 u_ACS01( .clkS (clkA), .clkD (clkB), .d (inputA), .reset_n (reset_n));"
The following 1-bit expression is connected to 8-bit port "d" of module
"rule_Ac_sync01", instance "u_ACS01".
Expression: inputA
Instantiated module defined at: "../RTL/rule_Ac_sync01.v", 1
Use +lint=PCWM for more details.
Warning-[PCWM-W] Port connection width mismatch
../RTL/training.v, 42
"CSCR u_CSCR( .clkS (clkE), .clkD (clkF), .d (inputA), .reset_n (reset_n));"
The following 1-bit expression is connected to 8-bit port "d" of module
"CSCR", instance "u_CSCR".
Expression: inputA
Instantiated module defined at: "../RTL/check_clock_relation.v", 2
Use +lint=PCWM for more details.
Warning-[PCWM-W] Port connection width mismatch
../RTL/training.v, 46
"rule_Ac_datahold01a u_ACDH01( .clkS (clkSrc), .rstS (rstS), .clkD (clkDest), .rstD (rstD), .dS (inputA), .outD (rule_Ac_datahold01a_out));"
The following 1-bit expression is connected to 8-bit port "dS" of module
"rule_Ac_datahold01a", instance "u_ACDH01".
Expression: inputA
Instantiated module defined at: "../RTL/rule_Ac_datahold01a.v", 2
Use +lint=PCWM for more details.
Warning-[PCWM-W] Port connection width mismatch
../RTL/training.v, 46
"rule_Ac_datahold01a u_ACDH01( .clkS (clkSrc), .rstS (rstS), .clkD (clkDest), .rstD (rstD), .dS (inputA), .outD (rule_Ac_datahold01a_out));"
The following 1-bit expression is connected to 8-bit port "outD" of module
"rule_Ac_datahold01a", instance "u_ACDH01".
Expression: rule_Ac_datahold01a_out
Instantiated module defined at: "../RTL/rule_Ac_datahold01a.v", 2
Use +lint=PCWM for more details.
Warning-[PCWM-W] Port connection width mismatch
../RTL/aslp128x8secwr.v, 118
"aslp128x8secwr_storage u_aslp128x8secwr_storage( .clock (wr_clock), .scan_mode (scan_mode), .wr_address (wr_address), .wr_data (wr_data), .wr_write (wr_access), .rd_address (rd_address), .rd_data (rd_data));"
The following 1-bit expression is connected to 8-bit port "rd_data" of
module "aslp128x8secwr_storage", instance "u_aslp128x8secwr_storage".
Expression: rd_data
Instantiated module defined at: "../RTL/aslp128x8secwr.v", 560
Use +lint=PCWM for more details.
Info: Invoking Simon...
Info: Simon VCS Start
Warning-[SM_URMI] Unresolved module instance in design.
../RTL/training.v, 36
Module definition 'as8x8fsec' of instance 'u_as8x8fsec' is not found in the
design
Note-[SM_EMPTY_DU] Marking empty Module/Entity as blackbox
../RTL/rule_Clock_info03a.v, 27
Module/Entity 'BBOX_CLOCK' is marked as a blackbox because it is empty
=======================================================
VCS CPU Time(s) :0.35
SIMON CPU Time(s) :0.64
SIMON Total Time(s) :0.24
Peak Memory(MB) :459
=======================================================
Info: Simon VCS Finished
Info: Simon call complete
Info: Exiting after Simon Analysis
Verdi KDB elaboration done and the database successfully generated: 0 error(s), 0 warning(s)
# Gate Counts
Number of Flat Instances = 3644
Number of Operator = 3642
Number of Libcells = 0
Number of Black-Box Instances = 2
Number of FlipFlop BitWise = 1481
Number of Latch Bitwise = 129
Number of Nand BitWise = 2
Number of Comb logic = 1053
1
#### Auto inferring clock and resets
infer_setup -type clock
1
write_inferred_setup -file ../SDC/autoclock.sdc -type clock
1
infer_setup -type reset
1
write_inferred_setup -file ../SDC/autoreset.sdc -type reset
1
#### User provided SDC files
read_sdc training.sdc
1
#### Running checks in VC CDC
check_cdc -type setup
[Error] CLKPROP_NO_CLK: No clock found in the SDC file
SDC files does not have any create_clock or create_generated_clock command.
check_cdc command resulted in 1 Error, 0 Warning, 0 Info message(s)
use report_cdc for more info3、在vc_static_shell中启动GUI以查看读取结果。
vc_static_shell> start_gui由于此时GUI是以VCST First Mode而不是Verdi First Mode打开的，两个窗口将被打开，其中一个用于查看标签(Tag)，另一个用于查看源代码，如图1和图2所示。
图1 标签查看窗口
图2 源代码查看窗口
4、查看并解决未解析模块警告（SM_URMI标签，表示完全无法找到模块定义）和黑盒模块信息（SM_EMPTY_DU标签，表示只有端口定义的空模块），图3展示了SM_URMI标签。
图3 SM_URMI标签
取消注释filelist文件training.f中第7行的as8x8fsec.v文件，取消注释vc_cdc.tcl文件第3行中的命令set_blackbox -design BBOX_CLOCK。
5、由于此时读取的约束文件training.sdc为空，设计中未定义约束条件，用户需要先为设计定义约束再启动CDC分析，使用下面的命令将一个预定义的约束文件复制到实验目录中（此操作会覆盖目录中已有的training.sdc文件）。
% cp ../SDC/.golden/training.sdc training.sdc
接着打开training.sdc文件，并注释掉以下几行：
- 第12行：create_clock -name clkH -period $DEFAULT_PERIOD {clkH}
- 第28行：set_clock_groups -asynchronous -group { clkH }
- 第46行：set_case_analysis 0 Clock_info05_sel
- 第49行：set_input_delay 10 inputA -clock "clkSrc"到最后
编辑完成后保存退出并使用以下命令重新运行VC Spyglass并查看SM_URMI标签和SM_EMPTY_DU标签是否消失。
% vc_static_shell -f vc_cdc.tcl
6、若要查看CDC违规情况，在命令行中运行以下命令，结果如下所示。
vc_static_shell> report_cdc -----------------------------------------------------------------------------
Management Summary
-----------------------------------------------------------------------------
Stage Family Fatals Errors Warnings Infos
----- --------- -------- -------- -------- --------
SETUP CLKPROP 0 23 0 38
SETUP RESET 0 23 6 21
----- --------- -------- -------- -------- --------
Total 0 46 6 59
-----------------------------------------------------------------------------
Tree Summary
-----------------------------------------------------------------------------
Severity Stage Tag Count
-------- ----- ----------------------------------- -----
error SETUP SETUP_ASYNC_CLOCK_OVERLAP 2
error SETUP SETUP_CLOCK_GLITCH 2
error SETUP SETUP_CLOCK_UNDECL 2
error SETUP SETUP_INPUT_MULTICLOCK_LOAD 4
error SETUP SETUP_PORT_PARTIALLY_CONSTRAINED 4
error SETUP SETUP_PORT_UNCONSTRAINED 9
error SETUP SETUP_RESET_ASSERT_MISSING 23
warning SETUP SETUP_RESET_DRIVING_NON_ASYNC_PIN 6
info SETUP SETUP_BBOXPIN_CONSTRAINED 1
info SETUP SETUP_CLOCK_PROPAGATED 11
info SETUP SETUP_DATA_CONSTANT 13
info SETUP SETUP_PORT_CONSTRAINED 9
info SETUP SETUP_PORT_IGNORED 4
info SETUP SETUP_RESET_INFER 13
info SETUP SETUP_RESET_PROPAGATED 8
-------- ----- ----------------------------------- -----
Total 1117、SETUP_PORT_UNCONSTRAINED标签表示存在未添加约束的端口，再次启动GUI进行查看，如图4所示。
vc_static_shell> start_gui
图4 SETUP_PORT_UNCONSTRAINED标签
用户可以看到未添加约束的端口列表及其潜在的时钟源（根据其扇出到达的有时钟约束的时序单元的时钟域推断），可以逐行检查并相应地添加约束，下面以端口inputA为例进行查看。
8、若违规项开头出现与门
图标，表示可查看对应的电路原理图，选择inputA违规项，然后点击窗口中的New Violation Schematic或者右键单击违规并在菜单中选择New Violation Schematic或者使用Ctrl+N快捷键，如图5所示，即可打开原理界面查看该违规的相关情况，如图6所示。
图5 打开违规的原理图
图6 违规的原理图
打开约束文件training.sdc，取消第49到最后的注释，重新运行VC Spyglass并查看SETUP_PORT_UNCONSTRAINED标签是否消失。
9、可以看出SETUP_PORT_UNCONSTRAINED标签依然存在，端口clkH还未被约束，且SETUP_CLOCK_UNDECL标签表示存在未定义时钟的时钟路径，下面以线网clkH为例进行查看，如图7所示。
图7 违规的原理图
打开约束文件training.sdc，取消第12行和第28行的注释，重新运行VC Spyglass并查看SETUP_PORT_UNCONSTRAINED标签和SETUP_CLOCK_UNDECL标签是否消失。
10、SETUP_ASYNC_CLOCK_OVERLAP标签表示两个或多个来自不同时钟域的时钟发生重叠，下面以u_CI05/clk_mux为例进行查看，如图8所示。
图8 违规的原理图
可以看出两个时钟通过多路选择器进行了汇聚，应当为该选择器设置约束，使其只选择一个时钟。可以像之前那样，打开约束文件training.sdc，取消第46行的注释，也可以按照下面的步骤使用约束编辑器完成相同操作，如图9所示。
(a) 在违规示意图中，右键点击选择器的选择引脚。
(b) 在右键菜单中点击Set Constraints...。
(c) 从下拉菜单中选择set_case_analysis，并填写数值和对象字段。
(d) 点击Generate以及Append，查看约束文件确认是否已更新，并重新运行VC Spyglass，查看SETUP_ASYNC_CLOCK_OVERLAP标签是否消失。
图9 添加约束
写在最后
为了完成设计的设置，用户也可以使用工具提供的自动时钟和复位识别功能，但建议在应用CDC分析中的约束之前，先检查每个自动识别出的时钟/复位信号是否正确，vc_cdc.tcl中的以下命令用于产生自动时钟和复位约束文件。
infer_setup -type clock
write_inferred_setup -file ../SDC/autoclock.sdc -type clock
infer_setup -type reset
write_inferred_setup -file ../SDC/autoreset.sdc -type reset 实验二
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