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ORCIDShekhar Borkar
- > Home > Persons > Shekhar Borkar
Publications
- 2015
[j40]Gregory K. Chen, Mark A. Anders, Himanshu Kaul, Sudhir Satpathy, Sanu K. Mathew, Steven Hsu, Amit Agarwal, Ram Krishnamurthy, Vivek De, Shekhar Borkar:
A 340 mV-to-0.9 V 20.2 Tb/s Source-Synchronous Hybrid Packet/Circuit-Switched 16 × 16 Network-on-Chip in 22 nm Tri-Gate CMOS. IEEE J. Solid State Circuits 50(1): 59-67 (2015)- 2014
- [c69]Gregory K. Chen, Mark A. Anders, Himanshu Kaul, Sudhir Satpathy, Sanu K. Mathew, Steven K. Hsu, Amit Agarwal, Ram K. Krishnamurthy, Shekhar Borkar, Vivek De:
16.1 A 340mV-to-0.9V 20.2Tb/s source-synchronous hybrid packet/circuit-switched 16×16 network-on-chip in 22nm tri-gate CMOS. ISSCC 2014: 276-277 - 2013
- [j38]Farhana Sheikh
, Sanu Mathew, Mark A. Anders, Himanshu Kaul, Steven Hsu, Amit Agarwal, Ram K. Krishnamurthy, Shekhar Borkar:
A 2.05 GVertices/s 151 mW Lighting Accelerator for 3D Graphics Vertex and Pixel Shading in 32 nm CMOS. IEEE J. Solid State Circuits 48(1): 128-139 (2013) - 2012
- [c64]Himanshu Kaul, Mark A. Anders, Steven Hsu, Amit Agarwal, Ram Krishnamurthy, Shekhar Borkar:
Near-threshold voltage (NTV) design: opportunities and challenges. DAC 2012: 1153-1158 - [c61]Himanshu Kaul, Mark A. Anders, Sanu Mathew, Steven Hsu, Amit Agarwal, Farhana Sheikh, Ram Krishnamurthy, Shekhar Borkar:
A 1.45GHz 52-to-162GFLOPS/W variable-precision floating-point fused multiply-add unit with certainty tracking in 32nm CMOS. ISSCC 2012: 182-184 - [c60]Farhana Sheikh, Sanu Mathew, Mark A. Anders, Himanshu Kaul, Steven Hsu, Amit Agarwal, Ram Krishnamurthy, Shekhar Borkar:
A 2.05GVertices/s 151mW lighting accelerator for 3D graphics vertex and pixel shading in 32nm CMOS. ISSCC 2012: 184-186 - [c58]Steven Hsu, Amit Agarwal, Mark A. Anders, Himanshu Kaul, Sanu Mathew, Farhana Sheikh, Ram Krishnamurthy, Shekhar Borkar:
A 2.8GHz 128-entry × 152b 3-read/2-write multi-precision floating-point register file and shuffler in 32nm CMOS. VLSIC 2012: 118-119 - 2010
- [j32]Himanshu Kaul, Mark A. Anders, Sanu Mathew, Steven Hsu, Amit Agarwal, Ram Krishnamurthy, Shekhar Borkar:
A 300 mV 494GOPS/W Reconfigurable Dual-Supply 4-Way SIMD Vector Processing Accelerator in 45 nm CMOS. IEEE J. Solid State Circuits 45(1): 95-102 (2010) - [c53]Mark A. Anders, Himanshu Kaul, Steven Hsu, Amit Agarwal, Sanu Mathew, Farhana Sheikh, Ram Krishnamurthy, Shekhar Borkar:
A 4.1Tb/s bisection-bandwidth 560Gb/s/W streaming circuit-switched 8×8 mesh network-on-chip in 45nm CMOS. ISSCC 2010: 110-111 - [c51]Amit Agarwal, Sanu Mathew, Steven Hsu, Mark A. Anders, Himanshu Kaul, Farhana Sheikh, Rajaraman Ramanarayanan, Suresh Srinivasan, Ram Krishnamurthy, Shekhar Borkar:
A 320mV-to-1.2V on-die fine-grained reconfigurable fabric for DSP/media accelerators in 32nm CMOS. ISSCC 2010: 328-329 - 2009
- [j31]Himanshu Kaul, Mark A. Anders, Sanu K. Mathew, Steven Hsu, Amit Agarwal, Ram K. Krishnamurthy, Shekhar Borkar:
A 320 mV 56 μW 411 GOPS/Watt Ultra-Low Voltage Motion Estimation Accelerator in 65 nm CMOS. IEEE J. Solid State Circuits 44(1): 107-114 (2009) - [c46]Himanshu Kaul, Mark A. Anders, Sanu Mathew, Steven Hsu, Amit Agarwal, Ram Krishnamurthy, Shekhar Borkar:
A 300mV 494GOPS/W reconfigurable dual-supply 4-Way SIMD vector processing accelerator in 45nm CMOS. ISSCC 2009: 260-261 - 2008
- [j27]Mark A. Anders, Sanu K. Mathew, Steven Hsu, Ram K. Krishnamurthy, Shekhar Borkar:
A 1.9 Gb/s 358 mW 16-256 State Reconfigurable Viterbi Accelerator in 90 nm CMOS. IEEE J. Solid State Circuits 43(1): 214-222 (2008) - [c42]Himanshu Kaul, Mark A. Anders, Sanu Mathew, Steven Hsu, Amit Agarwal, Ram Krishnamurthy, Shekhar Borkar:
A 320mV 56μW 411GOPS/Watt Ultra-Low Voltage Motion Estimation Accelerator in 65nm CMOS. ISSCC 2008: 316-317 - 2007
- [c38]Mark A. Anders, Sanu Mathew, Steven Hsu, Ram Krishnamurthy, Shekhar Borkar:
A 1.9Gb/s 358mW 16-to-256 State Reconfigurable Viterbi Accelerator in 90nm CMOS. ISSCC 2007: 256-600 - 2006
- [j24]Steven K. Hsu, Sanu K. Mathew, Mark A. Anders, Bart R. Zeydel, Vojin G. Oklobdzija, Ram K. Krishnamurthy, Shekhar Y. Borkar:
A 110 GOPS/W 16-bit multiplier and reconfigurable PLA loop in 90-nm CMOS. IEEE J. Solid State Circuits 41(1): 256-264 (2006) - [j23]Chris H. Kim, Kaushik Roy, Steven Hsu, Ram Krishnamurthy, Shekhar Borkar:
A process variation compensating technique with an on-die leakage current sensor for nanometer scale dynamic circuits. IEEE Trans. Very Large Scale Integr. Syst. 14(6): 646-649 (2006) - [c35]Steven K. Hsu, Amit Agarwal, Mark A. Anders, Sanu Mathew, Ram Krishnamurthy, Shekhar Borkar:
An 8.8GHz 198mW 16x64b 1R/1W variationtolerant register file in 65nm CMOS. ISSCC 2006: 1785-1797 - 2005
- [c32]Chris H. Kim, Steven Hsu, Ram Krishnamurthy, Shekhar Borkar, Kaushik Roy:
Self Calibrating Circuit Design for Variation Tolerant VLSI Systems. IOLTS 2005: 100-105 - [c31]Steven Hsu, Amit Agarwal, Kaushik Roy, Ram Krishnamurthy, Shekhar Borkar:
An 8.3GHz dual supply/threshold optimized 32b integer ALU-register file loop in 90nm CMOS. ISLPED 2005: 103-106 - 2003
- [j11]Steven Hsu, Atila Alvandpour, Sanu Mathew, Shih-Lien Lu, Ram K. Krishnamurthy, Shekhar Borkar:
A 4.5-GHz 130-nm 32-KB L0 cache with a leakage-tolerant self reverse-bias bitline scheme. IEEE J. Solid State Circuits 38(5): 755-761 (2003) - [c21]Manoj Sinha, Steven Hsu, Atila Alvandpour, Wayne P. Burleson, Ram Krishnamurthy, Shekhar Borkar:
Low voltage sensing techniques and secondary design issues for sub-90nm caches. ESSCIRC 2003: 413-416 - [c20]Bhaskar Chatterjee, Manoj Sachdev, Steven Hsu, Ram Krishnamurthy, Shekhar Borkar:
Effectiveness and scaling trends of leakage control techniques for sub-130nm CMOS technologies. ISLPED 2003: 122-127
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