• case-insensitive prefix search: default
  e.g., sig matches "SIGIR" as well as "signal"
• exact word search: append dollar sign ($) to word
  e.g., graph$ matches "graph", but not "graphics"
• boolean and: separate words by space
  e.g., codd model
• boolean or: connect words by pipe symbol (|)
  e.g., graph|network

Update May 7, 2017: Please note that we had to disable the phrase search operator (.) and the boolean not operator (-) due to technical problems. For the time being, phrase search queries will yield regular prefix search result, and search terms preceded by a minus will be interpreted as regular (positive) search terms.

found 15 matches

• 1995
• 
  K'Andrea C. Bickerstaff, Michael J. Schulte, Earl E. Swartzlander Jr.:
  Parallel reduced area multipliers. J. VLSI Signal Process. 9(3): 181-191 (1995)
• 
  Phillip Duncan, Ken Kindsfater, Lynette Liu, Rajeev Jain:
  Strategies for design automation of high speed digital filters. J. VLSI Signal Process. 9(1-2): 105-119 (1995)
• 
  Gert Goossens, Dirk Lanneer, Marc Pauwels, Francis Depuydt, Koen Schoofs, Augusli Kifli, Marco Cornero, Paolo Petroni, Francky Catthoor, Hugo De Man:
  Integration of medium-throughput signal processing algorithms on flexible instruction-set architectures. J. VLSI Signal Process. 9(1-2): 49-65 (1995)
• 
  Ramaswamy Govindarajan, Guang R. Gao:
  Rate-optimal schedule for multi-rate DSP computations. J. VLSI Signal Process. 9(3): 211-232 (1995)
• 
  Paolo Ienne, Marc A. Viredaz:
  GENES IV: A bit-serial processing element for a multi-model neural-network accelerator. J. VLSI Signal Process. 9(3): 257-273 (1995)
• 
  Dominique Lavenier, Frédéric Raimbault, Patrice Frison:
  I/O and computation overlap on SIMD systolic arrays. J. VLSI Signal Process. 9(3): 153-165 (1995)
• 
  Jef L. van Meerbergen, Paul E. R. Lippens, Wim F. J. Verhaegh, Albert van der Werf:
  PHIDEO: High-level synthesis for high throughput applications. J. VLSI Signal Process. 9(1-2): 89-104 (1995)
• 
  Chetana Nagendra, Robert Michael Owens, Mary Jane Irwin:
  Digit pipelined arithmetic on fine-grain array processors. J. VLSI Signal Process. 9(3): 193-209 (1995)
• 
  Keshab K. Parhi:
  High-level algorithm and architecture transformations for DSP synthesis. J. VLSI Signal Process. 9(1-2): 121-143 (1995)
• 
  Pierre G. Paulin, Clifford Liem, Trevor C. May, Shailesh Sutarwala:
  DSP design tool requirements for embedded systems: A telecommunications industrial perspective. J. VLSI Signal Process. 9(1-2): 23-47 (1995)
• 
  José Luis Pino, Soonhoi Ha, Edward A. Lee, Joseph T. Buck:
  Software synthesis for DSP using ptolemy. J. VLSI Signal Process. 9(1-2): 7-21 (1995)
• 
  Wee-Chiew Tan, Teresa H.-Y. Meng:
  A low-power high performance polygon renderer for computer graphics. J. VLSI Signal Process. 9(3): 233-255 (1995)
• 
  Ingrid Verbauwhede, Jan M. Rabaey:
  Guest editor's introduction design environments for DSP. J. VLSI Signal Process. 9(1-2): 5-6 (1995)
• 
  Ingrid Verbauwhede, Jan M. Rabaey:
  Synthesis for real time systems: Solutions and challenges. J. VLSI Signal Process. 9(1-2): 67-88 (1995)
• 
  Benjamin W. Wah:
  Guest editor's introduction. J. VLSI Signal Process. 9(3): 151 (1995)