Michael Windig

EU Approves €920M in State Aid for Infineon Technologies’s €3.5B Chip Plant in Dresden The European Commission has approved €920 million in German state aid to support Infineon’s €3.5 billion MEGAFAB-DD project in Dresden. This plant, set to reach full capacity by 2031, will manufacture a broad range of semiconductors for industrial, automotive, and consumer applications. This move aligns with the European Chips Act, which aims to strengthen Europe’s semiconductor supply chain, resilience, and technological autonomy. The EU has allocated €15 billion for public and private semiconductor projects by 2030, reinforcing its commitment to securing advanced chip manufacturing. Infineon, in turn, has committed to R&D investment in next-generation chips and supporting crisis preparedness through priority-rated orders in supply shortages. As global chipmakers continue expanding capacity with government support, how will this impact Europe's position in the semiconductor race? Thanks again to Reuters for the full article with more background and insights click the source link in the comments below. #ChipDesign,#SemiconductorManufacturing, #VLSI, #Lithography, #ICPackaging #Semiconductors #Infineon #ChipsAct #Manufacturing #EU

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Infineon brings RISC-V to the automotive industry. Thrilled to announce that our next-gen AURIX™ microcontrollers will be based on RISC-V and that we will introduce an industry-first automotive RISC-V virtual prototype at the @embeddedworld 2025.   Future automotive microcontrollers require a combination of real-time control, powerful data processing, high-speed networking, AI, and top-notch security. Infineon combines its proven microcontroller expertise with RISC-V open source technology to address these complex requirements.   As the global leader in automotive microcontrollers, we are committed to make RISC-V the open standard for the automotive industry.   Actively working to accelerate RISC-V standardization, industrialization, and ecosystem we prove our commitment with our industry-first automotive RISC-V virtual prototype. Thus, we enable seamless software development before hardware availability and speed up the development of a vibrant software and tool ecosystem together with our partners.   Infineon makes RISC-V available for future mobility.   Come and see us at the Embedded World in hall 4A at booth 138. Catch further RISC-V details here: https://lnkd.in/dVyPkyxu Read Infineon’s press release here: https://lnkd.in/ddfyCX_t   #Infineon #digitalization #automotive #mobility #SoftwareDefinedVehicles #sdv #RISC_V #AutomotiveInnovation #AURIX #FutureOfMobility #EmbeddedWorld2025

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What is the difference between Wafer, Chip and Die? -> Wafer: The raw canvas. A wafer is a thin, circular slice of pure silicon—typically 200mm or 300mm in diameter—used as the base for fabricating integrated circuits. Think of it as the foundation where thousands of tiny circuits are etched layer by layer using advanced photolithography. Example: A polished silicon wafer before chip fabrication begins. -> Die: The core logic unit. A die is a single block of circuitry on that wafer—essentially one instance of the chip design. After the wafer is processed, it's cut into hundreds (or thousands) of dies, each capable of performing the full functionality intended (CPU core, memory controller, etc.). Example: One processor core on a multi-core CPU. -> Chip (or Package): The finished product. A chip is the packaged version of the die, complete with protective housing, heat spreaders, and pins or balls to interface with a PCB. It’s what gets shipped and installed in devices—from phones to servers. Example: An Intel Core i9 CPU installed on a motherboard. Visual analogy: The wafer is a pizza. Each die is a slice. The chip is that slice—boxed, wrapped, and ready to deliver. At Atoms, we focus on the final but most critical step—validating chips after packaging before they reach the world. Our platform TestFlow automates post-silicon validation, analyzes lab data, and helps teams bring robust chips to market faster. #Semiconductors #WaferToChip #ICDesign #ChipPackaging #PostSiliconValidation #ATOMS #TestFlow #ChipDesign #DiePrep #SiliconManufacturing #SemiconductorEngineering

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Femtum FIXES BROKEN CHIPS, INCREASING YIELD. In past OFC Conferences we have followed the progress of Optica Corporate member Femtum, who does amazing things with 3-micrometer femtosecond lasers. This year, they launched their Photonics Wafer Laser Trimming Solution. It addresses the photonics industry problem: costs are high because the yield is low. This system, which is built into a ficonTEC machine, offers a fast way to fix broken chips! So, I caught up with Louis-Rafaël Robichaud, CEO of Femtum, to get the live demo. He also explained that the process for automated chip CLEANING is in the advanced stages of testing with customers. (In fact, Optica members are encouraged to send them samples to test the system. No more Q-tips)   🔧 Built for wafer-level refractive index correction, the system demonstrated: Sub-millisecond waveguide correction Strong phase shifting with negligible loss Real-time monitoring via Femtum’s proprietary LIT software Significant improvement in Known Good Dies (KGD) yield Compatibility with platforms like ficonTEC. The laser trimming solution targets critical needs in: - Silicon Photonics - TFLN, Fused Silica, and Silicon Nitride - High-throughput environments demanding rapid prototyping and shorter time-to-market 🇨🇦 Developed in Quebec, Femtum’s innovation reflects its core mission: to unlock the full potential of mid-infrared lasers for industrial and scientific applications, from selective microprocessing to next-gen semiconductor production. Kudos to the Femtum team—Louis-Rafaël Robichaud, Carl Paquet, Vinh N. Dang, Jean-Philippe Bérubé, and Robert Baribault—for delivering a strong presence and sharp insights on the OFC show floor. Onward to 2026.

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Mini-Circuits announces product releases for 16 models of connectorized broadband #RF #highpower #amplifier modules. These are in addition to 600+ amplifier models that are already available in stock. This portfolio of broadband amplifier has operating frequencies from 10 MHz up to 2000 MHz and saturated output power levels as low as 1 W and as high as 50W. The products can be ordered with heatsink or without heatsink. The amplifiers are designed using state of the art #RFpower semiconductor technology. Built-in protection circuits for excessive voltage, power & temperature is implemented in these amplifier models to survive open and short conditions at the specified CW power on the data sheet. The high gain, ~50dB specification of the amplifier, allows it to work with any commercially available signal sources. These amplifiers can be used in a broad range of applications which includes RF #EMC testing for #automotive or #Industrial #IoT, Laser Drivers for #QuantumComputing, General Purpose #Instrumentation Amplifier for lab use, #Communications and various #wireless testing. For more information , visit link below. https://lnkd.in/eDMU2z_j #RFEngineering, #testandmeasurements, #radar, #milcom, #satcom, #telecom,

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UBM (Under Bump Metallization) Purpose: UBM is a critical layer in advanced semiconductor packaging, enabling reliable electrical and mechanical connections between the chip and solder bumps or copper pillars. Functions: Provides electrical interconnection, wetting for solder, diffusion barrier, and mechanical support. Prevents failures like delamination, solder voids, and electromigration. Applications: Used in Flip-Chip, Wafer-Level Packaging (WLP), Fan-Out WLP, 2.5D/3D IC stacking, and high-end 3D packaging (e.g., HBM, CoWoS). Materials: Multi-layer stacks: adhesion (Ti, TiW, Ta), seed/conductor (Cu), barrier (TiN, Ta, Ni), wetting (Au, Ag), and solder (Sn, SnAgCu). Etching: Selective etchants are used for each metal layer (e.g., HF+H₂O₂ for Ti, H₃PO₄+H₂O₂ for Cu, KI/I₂ for Au). Process control is crucial to avoid over-etching and ensure pad accuracy. Trends: Moving toward finer pitches (<50 μm), eco-friendly chemistries, cost reduction (less Au), and dry/plasma etching for better precision. Conclusion: UBM is foundational for next-gen semiconductor reliability, yield, and performance, especially as packaging becomes more complex and dense.

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