Oliver Achten

EU Approves €920M in State Aid for Infineon Technologies’s €3.5B Chip Plant in Dresden The European Commission has approved €920 million in German state aid to support Infineon’s €3.5 billion MEGAFAB-DD project in Dresden. This plant, set to reach full capacity by 2031, will manufacture a broad range of semiconductors for industrial, automotive, and consumer applications. This move aligns with the European Chips Act, which aims to strengthen Europe’s semiconductor supply chain, resilience, and technological autonomy. The EU has allocated €15 billion for public and private semiconductor projects by 2030, reinforcing its commitment to securing advanced chip manufacturing. Infineon, in turn, has committed to R&D investment in next-generation chips and supporting crisis preparedness through priority-rated orders in supply shortages. As global chipmakers continue expanding capacity with government support, how will this impact Europe's position in the semiconductor race? Thanks again to Reuters for the full article with more background and insights click the source link in the comments below. #ChipDesign,#SemiconductorManufacturing, #VLSI, #Lithography, #ICPackaging #Semiconductors #Infineon #ChipsAct #Manufacturing #EU

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What is the difference between Wafer, Chip and Die? -> Wafer: The raw canvas. A wafer is a thin, circular slice of pure silicon—typically 200mm or 300mm in diameter—used as the base for fabricating integrated circuits. Think of it as the foundation where thousands of tiny circuits are etched layer by layer using advanced photolithography. Example: A polished silicon wafer before chip fabrication begins. -> Die: The core logic unit. A die is a single block of circuitry on that wafer—essentially one instance of the chip design. After the wafer is processed, it's cut into hundreds (or thousands) of dies, each capable of performing the full functionality intended (CPU core, memory controller, etc.). Example: One processor core on a multi-core CPU. -> Chip (or Package): The finished product. A chip is the packaged version of the die, complete with protective housing, heat spreaders, and pins or balls to interface with a PCB. It’s what gets shipped and installed in devices—from phones to servers. Example: An Intel Core i9 CPU installed on a motherboard. Visual analogy: The wafer is a pizza. Each die is a slice. The chip is that slice—boxed, wrapped, and ready to deliver. At Atoms, we focus on the final but most critical step—validating chips after packaging before they reach the world. Our platform TestFlow automates post-silicon validation, analyzes lab data, and helps teams bring robust chips to market faster. #Semiconductors #WaferToChip #ICDesign #ChipPackaging #PostSiliconValidation #ATOMS #TestFlow #ChipDesign #DiePrep #SiliconManufacturing #SemiconductorEngineering

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Will the #DRAM ‘D1e’ Node be Added Before D0a? 💡 DRAM #technology nodes in the 10 nm class (19.9 nm ~ 10.0 nm) show D1x → D1y → D1z → D1a → D1b → D1c → D1d, and then the first sub-10 nm node is expected to be D0a with 9.x nm feature size (DRAM Technology Roadmap). Now, three big DRAM champions such as Samsung Semiconductor, SK hynix, and Micron Technology produce D1b (12.x ~ 13.x nm) and D1c (11.x ~ 12.x nm) DRAM devices. Would DRAM ‘D1e’ node be added before D0a? It depends on the design rule (D/R) of the D1d cell design. If D1d nodes have high-10 nm, such as 10.9 nm or 10.8 nm D/Rs, then D1e may be added before the single digit generation such as D0a. Regarding the DRAM technology node (D/R or feature size of each generation), nowadays, it’s a little confusing and difficult to define it accurately because it does not follow the cell size of 6F2. Based on the tilted active island pattern with 69 degrees to the WL, the cell size is equal to 7.8F2 rather than 6F2. For the 30nm, 2x, and 2y generations, #Micron's active half pitches are quite larger than #SKhynix's and #Samsung’s, however; since D1x, three DRAM players have almost the same nodes with a few ups and downs. For D1a or D1-alpha, Samsung D1a tech node (13.8 nm) is a lower number than SK hynix’s and Micron’s. Micron’s D1-beta has 13.04 nm D/R rather than 12nm-class, while the SK hynix D1b DRAM cell shows 12.65 nm D/R, and Samsung’s D1b has 12.54 nm. A big Thanks again to Jeongdong Choe and TechInsights for the full article with more background and insights via the link in the comments section - very good overview of all the current DRAM #Technologies 💡❤️🙏 #semiconductorindustry #semiconductormanufacturing #chip #chips #it #ic #innovation #korea #japan #taiwan #usa #china #ai #aiot #ev #server

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🔍 The Formal Verification Cold Start Problem You’ve read the spec. You’ve discussed with the designer. You think you understand the design… But now you’re staring at a blank SVA file wondering: “Where do I even begin?” If that feels familiar, welcome to the cold start problem of formal verification—and yes, we’ve all been there. 💡 The Fix: Start with Cover Properties Forget trying to prove everything from day one. Your goal is to observe behavior before you start proving constraints. 🎯 Real Example: FIFO Design When I was verifying a simple synchronous FIFO, I started like this: cover property (@(posedge clk) wr_en && !full); ✅ Covers a write happening when FIFO isn’t full cover property (@(posedge clk) rd_en && !empty); ✅ Covers a read when FIFO isn’t empty cover property (@(posedge clk) wr_en ##[1:5] rd_en); ✅ Covers a write followed by a read within 5 cycles That’s it. From there, I built ordering checks, flag assertions, and finally full correctness proofs. The key was just starting. 🧪 Design Exercise Plan (for You or Your Team) Try this simple cold-start exercise on a FIFO design: 🔹 Step 1 – Cover Activity Cover a write when not full Cover a read when not empty Cover write followed by read 🔹 Step 2 – Observe State Cover full and empty being reached Cover FIFO staying non-empty for N cycles Cover pointer wraparound 🔹 Step 3 – Simple Assertions assert property: write only when not full assert property: read only when not empty assert: empty and full never both high 📌 Just like in software: don’t over-engineer your first line of code. In formal, don’t overthink your first property. Momentum matters more than perfection. Start anywhere. Learn as you go. #FormalVerification #VLSI #FIFO #SVA #SystemVerilog #DesignVerification #Semiconductors #HardwareDesign #VerificationEngineer #FormalMethods #ColdStartProblem #TechTips

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Latency kills. Privacy matters. Power is precious. Infineon’s new whitepaper lays out how Edge AI flips the script on classical computing—bringing real-time intelligence to the edge. 💡 Why it matters: → ML models on microcontrollers → No cloud? No problem. → Smarter decisions, faster responses → Safer, more private interactions With PSOC™ Edge and DEEPCRAFT™, developers can build AI-powered products that learn, adapt, and evolve—right where the data lives. From smart agriculture to robotics, this is the future of embedded intelligence. 📄 Dive in: https://lnkd.in/gqC3jprg

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Another big milestone for Zero ASIC! Our Platypus family of open eFPGA just got a major upgrade in the relase of a set of heterogeneous eFPGAs with built in BRAM and DSP blocks. https://lnkd.in/e-HBARnG Platypus is the only eFPGA in the world guaranteeing: 100% open and standardized FPGA architectures 100% open source FPGA bitstream formats 100% open source FPGA development tools For the reasoning behind our open approach, check out the original Platypus announcement from earlier this year. https://lnkd.in/eyPxEUAX This awesome effort was led by Peter Grossmann, with tool chain contributions from Frederick Tombs, Wildebeest synthesis from Thierry Besson, and SiliconCompiler infrastructure from Peter Gadfort. With SoCs taking years to design and costing $100M - $1B to develop, I am always surprised more teams don't dedicate a portion of the silicon area to eFPGA logic. What's holding you back? Appreciate your thoughts and comments below.

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The European Commission said on Thursday it had approved a 920 million euro German state aid to Infineon Technologies for constructing a new semiconductor manufacturing plant in Dresden. The measure will allow Infineon (IFXGn.DE) to complete the MEGAFAB-DD project, which will produce a wide range of different types of chips, the Commission added.

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