
5.33 General-Purpose Memory Controller (GPMC)............................................................................................................. 100
5.34 GPMC Error Location Module (ELM)........................................................................................................................... 102
5.35 Global Timebase Counter (GTC)................................................................................................................................. 105
5.36 Inter-Integrated Circuit (I2C) Interface......................................................................................................................... 106
5.37 Improved Inter-Integrated Circuit (I3C) Interface......................................................................................................... 108
5.38 PRU_ICSSG ................................................................................................................................................................112
5.39 Power Sleep Controller (Main PSC).............................................................................................................................112
5.40 Power Sleep Controller in WKUP Domain (WKUP PSC).............................................................................................113
5.41 Multicore Shared Memory Controller(MSMC).............................................................................................................. 115
5.42 JTAG.............................................................................................................................................................................119
5.43 Multi-Standard HD Video Decoder (D5520MP2 DECODER).......................................................................................120
5.44 Multi-Standard HD Video Encoder (ENCODER)..........................................................................................................122
5.45 Graphics Accelerator (GPU)........................................................................................................................................ 124
5.46 Controller Area Network (MCAN).................................................................................................................................126
5.47 Multichannel Audio Serial Port (MCASP).....................................................................................................................129
5.48 Matrix Multiply Accelerator (MMA)............................................................................................................................... 131
5.49 MMR (Memory Mapped Registers).............................................................................................................................. 133
5.50 MSMC DRU..................................................................................................................................................................135
5.51 MSRAM........................................................................................................................................................................137
5.52 NAVSS CPTS...............................................................................................................................................................138
5.53 NAVSS Interrupt Aggregator........................................................................................................................................ 140
5.54 NAVSS Interrupt Router............................................................................................................................................... 141
5.55 NAVSS Mailbox............................................................................................................................................................143
5.56 NAVSS MCRC..............................................................................................................................................................145
5.57 NAVSS PVU.................................................................................................................................................................147
5.58 NAVSS RA Proxy......................................................................................................................................................... 149
5.59 NAVSS Spinlock...........................................................................................................................................................151
5.60 NAVSS Timer Manager................................................................................................................................................152
5.61 NAVSS UDMA..............................................................................................................................................................154
5.62 Page Based Address Translation Unit (PAT)................................................................................................................157
5.63 PBIST...........................................................................................................................................................................160
5.64 Peripheral Component Interconnect Express (PCIe) Subsystem................................................................................ 161
5.65 Peripheral Direct Memory Access (PDMA).................................................................................................................. 165
5.66 Power Supply............................................................................................................................................................... 167
5.67 PSRAM........................................................................................................................................................................ 169
5.68 PSROM........................................................................................................................................................................ 170
5.69 Dual-R5F MCU - Pulsar Subsystem............................................................................................................................ 172
5.70 Region-based Address Translation (RAT) Module.......................................................................................................177
5.71 Reset............................................................................................................................................................................179
5.72 SA2_UL........................................................................................................................................................................181
5.73 SMMU.......................................................................................................................................................................... 183
5.74 Multichannel Serial Peripheral Interface (MCSPI)........................................................................................................185
5.75 Timers.......................................................................................................................................................................... 187
5.76 Universal Asynchronous Receiver/Transmitter (UART)...............................................................................................189
5.77 Universal Flash Storage (UFS) Interface..................................................................................................................... 191
5.78 Universal Serial Bus (USB) Subsystem....................................................................................................................... 194
5.79 UTC..............................................................................................................................................................................197
5.80 VBUSM Timeout Gasket.............................................................................................................................................. 200
5.81 Vectored Interrupt Manager (VIM)................................................................................................................................202
5.82 Vision Pre-processing Accelerator (VPAC).................................................................................................................. 204
5.83 Video Processing Front End (VPFE)............................................................................................................................208
5.84 Voltage and Thermal Manager (VTM)..........................................................................................................................210
5.85 4-L SerDes (SERDES SIERRA).................................................................................................................................. 212
5.86 2-L SerDes (SERDES TORRENT)...............................................................................................................................214
6 DRA829/TDA4VM Management of Random Faults..........................................................................................................218
6.1 Fault Reporting...............................................................................................................................................................218
6.2 Safety Mechanism Categories....................................................................................................................................... 219
6.3 Description of Safety Mechanisms.................................................................................................................................219
7 An In-Context Look at this Safety Element out of Context.............................................................................................277
7.1 System Safety Concept Example – Integrated Cockpit with Navigation, Media and Audio........................................... 277
7.2 System Safety Concept Example – ADAS: Surround View Perception and Park Assist System.................................. 292
7.3 Reference to PMIC Integration Guide............................................................................................................................ 308
A Summary of Recommended Safety Mechanism Usage................................................................................................. 310
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2 DRA829/TDA4VM Safety Manual
Jacinto™ 7 Processors
Texas Instruments Jacinto™ 7 Family of Products
SPRUIR1 – DECEMBER 2021
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