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TC358749XBG
(H2C+)
Functional Specification
TOSHIBA
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H2C+ Functional Spec Confidential Page 2 of 341
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H2C+ Functional Spec Confidential Page 3 of 341
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HISTORY
Revision
Date
Note
Rev 0.72
10/08/13
1. Add 80-pin package, product#749 for HDMI Rx CSI-2Tx (H2C+)
2. Debug registers 0x6500, 0x6504, 0x6508, 0x650C, 0x6510, 0x6514, 0x6518, 0x651C
and 0x6520 all read "0", remove from spec.
3.
Rev 0.73
11/17/2013
1. Updated register fields to remove “??”
2. Typo fixed
3. Removing 0x85A5～0x85AE referring in register bit 0x8520[7] description
4. VPGM and REXT description
Rev 0.74
12/25/2013
0x040C register bit15 correct
TC358749XBG Functional Specification Rev 0.74
H2C+ Functional Spec Confidential Page 4 of 341
Copyright © 2005-2010 MIPI Alliance, Inc. All rights reserved.
MIPI Alliance Member Confidential.
All rights reserved. This material is reprinted with the permission of the MIPI Alliance, Inc. No part(s) of this document may be disclosed, reproduced
or used for any purpose other than as needed to support the use of the products of Toshiba America Electronic Components, Inc.
REFERENCES
1. MIPI D-PHY, “MIPI_D-PHY_specification_v01-00-00, May 14, 2009”
2. MIPI CSI-2, “MIPI Alliance Specification for Display Serial Interface (CSI-2) Version 1.1
Revision 22 Nov 2011”
3. HDMI, “High-Definition Multimedia Interface Specification Version 1.4b March 4, 2010”
4. I2C bus specification, version 2.1, January 2000, Philips Semiconductor
5. IEC 60958, Digital Audio Interface, First Edition, 1999
6. IEC 61937, Digital audio – Interface for non-linear PCM encoded audio bit streams
7. MIPI SlimBus, “MIPI Alliance Specification for Serial Low-power Inter-chip Media Bus
(SLIMbus) Version 1.01.01 – 14 July 2008”
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or used for any purpose other than as needed to support the use of the products of Toshiba America Electronic Components, Inc.
Table of content
1 Overview ...................................................................................................................... 22
2 Features ....................................................................................................................... 23
3 External Pins ................................................................................................................ 27
3.1 Pin Summary .......................................................................................................... 29
3.2 Pin Layout .............................................................................................................. 29
4 Major Functional Blocks ............................................................................................. 30
4.1 HDMI-RX ................................................................................................................ 31
4.1.1 3D Support .................................................................................................................. 31
4.1.2 Color Space Conversion (RGB to YCbCr) .................................................................. 31
4.1.2.1 RGB888 to YCbCr422 ......................................................................................... 32
4.1.2.2 RGB888 to YCbCr444 ......................................................................................... 32
4.1.2.3 YCbCr444 to YCbCr422 ...................................................................................... 32
4.1.2.4 YCbCr422 to YCbCr444 ...................................................................................... 32
4.2 Video Processing Module ....................................................................................... 32
4.2.1 De-Interlacer ............................................................................................................... 33
4.2.2 Scalar .......................................................................................................................... 33
4.2.3 Color Space Conversion (YCbCr to RGB) .................................................................. 35
4.3 CSI-2 TX Protocol ................................................................................................... 35
4.3.1 CSI-2 TX Interface Block ............................................................................................ 39
4.3.2 CSI-2 TX Packet Format ............................................................................................. 40
4.3.3 Frame Count ............................................................................................................... 41
4.3.4 Checksum Generation ................................................................................................ 41
4.3.5 CSI-2 TX One Frame Operation ................................................................................. 42
4.4 CEC Controller ....................................................................................................... 42
4.4.1 Receive Operation Sequence ..................................................................................... 42
4.4.1.1 Noise cancellation time ....................................................................................... 43
4.4.1.2 Start bit detection................................................................................................. 43
4.4.1.3 Waveform Error Detection ................................................................................... 44
4.4.1.4 Data sampling timing ........................................................................................... 44
4.4.2 Transmit Operation Sequence .................................................................................... 45
4.4.2.1 Wait Time for Bus to be Free .............................................................................. 45
4.4.2.2 Transmission Timing ........................................................................................... 46
4.4.3 Arbitration lost ............................................................................................................. 46
4.4.4 Low level functions ...................................................................................................... 47
4.5 Audio Output Function ............................................................................................ 48
4.5.1 I2S Interface ................................................................................................................ 48
4.5.2 TDM (Time Division Multiplexed) Audio Interface ...................................................... 48
4.5.3 SPDIF Audio ............................................................................................................... 49
4.5.4 SLIMbus Audio ............................................................................................................ 49
4.5.4.1 SlimBus Clock Generation .................................................................................. 53
4.5.4.1.1 SlimBus Clock from PLL11 or External ActiveFramer ............................................... 53
4.5.4.1.2 SlimBus Clock from HDMI Rx ................................................................................... 54
4.5.5 IEC 60958/61937 over I2S .......................................................................................... 56
4.5.5.1 HBR Split over I2S............................................................................................... 58
4.5.6 Audio PLL LPF Configuration ..................................................................................... 60
4.6 InfraRed (IR) Interface ............................................................................................ 61
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