THCV242_Rev100_E.pdf_thcv241资源-CSDN下载

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THCV242 is designed to support 1080p60 2Mpixel uncompressed video data over 15m 100ohm differential STP or single-end 50ohm Coaxial cable with 4 in-line connectors between camera and processor by V-by-One® HS THCV242是一款专为高清视频传输设计的串行接收器，支持通过V-by-One® HS技术在15米的100欧姆差分STP或50欧姆同轴电缆上无压缩地传输1080p60分辨率的2M像素视频数据，最多可有4个线路连接器。这款芯片主要应用于摄像头与处理器之间的高速连接，并且兼容MIPI CSI-2接口标准。 THCV242支持MIPI CSI-2接口，能够提供1、2或4条数据通道的输出，每条通道的最大数据传输速率可达1.2Gbps。它还支持虚拟通道功能，增强了数据传输的灵活性。此外，MIPI的第二个端口可以用于数据复制和分布。THCV242的一个高速V-by-One® HS通道能传输高达1080p60帧/秒的视频，单通道最大串行数据速率为4Gbps。第二输入通道则设计用于处理高动态范围（HDR）的大容量数据或实现相机切换体验。该设备具备远程控制和监控摄像头模块的功能，可以通过GPIO或1Mbps的2线串行接口与主处理器单元（MPU）通信。为了确保硬件功能的安全性，THCV242集成了多种故障和错误检测功能，如CRC校验，并能够进行错误通知。其内部结构包括MIPI CSI-2数据发送4通道、时钟发送2端口、V-by-One® HS主链路接收2通道和子链路2通道，以及GPIO和UART控制监测接口。IO电压范围广泛，支持1.7V至3.6V。此外，THCV242采用QFN64封装，尺寸为9x9mm，引脚间距为0.5mm，并带有扩展焊盘。 THCV242的特性还包括帧同步远程供电方案，用于多摄像头流同步，以及2线串行接口的1Mbps桥接功能。通过这些特性，THCV242能够有效地在不同设备间切换和分配视频流，同时确保数据的完整性和系统的稳定性。 THCV242是高性能视频传输和接口转换的理想选择，尤其适用于需要高分辨率和高帧率的高清视频应用，如安防监控、无人机摄影、自动驾驶汽车等领域。它的兼容性和强大的功能使其能够在各种复杂环境中实现可靠的数据传输。

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THCV242_ Rev.1.00_E

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THCV242

SerDes receiver with bi-directional transceiver

1. General Description

THCV242 is designed to support 1080p60 2Mpixel

uncompressed video data over 15m 100ohm

differential STP or single-end 50ohm Coaxial cable

with 4 in-line connectors between camera and

processor by V-by-One® HS.

THCV242 supports a MIPI CSI-2. Each CSI-2 data

lane can transmit up to 1.2Gbps/lane. Virtual channel

is supported. MIPI 2nd port output supports data

copy and distribution.

One high-speed V-by-One® HS lane can transmit up

to 1080p60fps. The maximum serial data rate is

4Gbps/lane. 2nd input lane supports HDR large

amount of data or camera switch experience.

THCV242 is capable to control and monitor remote

camera module from MPU via GPIO or 1Mbps 2-

wire serial interface.

Several fault and error detection function including

CRC provides hardware functional safety design.

2. Features

 MIPI CSI-2 with 1,2 or 4-lane output

 MIPI D-PHY supports 80Mbps~1.2Gbps

 MIPI Virtual channel supported

 Video formats: RAW8/10/12/14/16/20,

YUV422/420, RGB888/666/565, JPEG, User-

defined generic 8-bit

 V-by-One® HS 400Mbps~4Gbps x2lane

 V-by-One® HS standard version1.5

 Video stream switch and copy/distribution

 Frame sync remote supply scheme for multiple

camera stream synchronization

 Wide range IO voltage from 1.7V to 3.6V

 2-wire serial interface 1Mbps bridge function

 Remote GPIO/UART control and monitoring

 Error detection including CRC and notification

 QFN64 9x9mm 0.5mm pitch Exp-pad package

3. Block Diagram

MTX0P

MTX0N

CSI2 / Formatter

Deserializer

CDR

Controls

MTXCLK0P

MTXCLK0N

OSC

MTX1P

MTX1N

Settings

2-wire

serial I/F

RX0P

RX0N

RCM1P

RCM1N

MIPI CSI-2

Data Tx 4-lane

Clock Tx 2-port

THCV242

V-by-One® HS

Main-Link

Rx 2-lane

Sub-Link 2-lane

MTX2P

MTX2N

MTX3P

MTX3N

GPIO

RX1P

RX1N

RCM0P

RCM0N

MTXCLK1P

MTXCLK1N

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Contents page

1. General Description ......................................................................................................................................... 1

2. Features ........................................................................................................................................................... 1

3. Block Diagram ................................................................................................................................................ 1

4. Pin Configuration ............................................................................................................................................ 4

5. Pin Description ................................................................................................................................................ 5

6. Functional Description .................................................................................................................................... 6

6.1. Functional Overview ............................................................................................................................... 6

6.2. HTPDN/LOCKN ..................................................................................................................................... 6

6.3. V-by-One® HS input setting ................................................................................................................... 8

6.3.1. MPRF (Main-Link PRivate Format) ............................................................................................... 8

6.3.2. V-by-One® HS standard format ...................................................................................................... 9

6.4. Header/Packet/Sync Pre-processing ...................................................................................................... 13

6.5. Data stream handling ............................................................................................................................. 14

6.6. MIPI output setting ................................................................................................................................ 15

6.7. 2-wire serial interface ............................................................................................................................ 18

6.7.1. 2-wire serial I/F slave Device ID ................................................................................................... 18

6.7.2. 2-wire serial Read/Write access to local Register .......................................................................... 19

6.8. 2-wire serial I/F Watch Dog Timer ........................................................................................................ 20

6.9. Register Auto Checksum diagnosis ....................................................................................................... 20

6.10. Sub-Link setting ................................................................................................................................ 21

6.10.1. Sub-Link 2-wire Set and Trigger mode (2-wire Normal mode) .................................................... 22

6.10.2. Sub-Link 2-wire Pass Through mode ............................................................................................ 25

6.10.3. Sub-Link transaction time accuracy Improvement ........................................................................ 28

6.11. GPIO setting .......................................................................................................................................... 29

6.11.1. GPIO as secondary 2-wire port ..................................................................................................... 30

6.11.2. Register GPIO ............................................................................................................................... 30

6.11.3. Through GPIO Sub-Link Polling input/output .............................................................................. 31

6.12. Internal Error / status signal monitoring ERR0/ERR1 pin output ..................................................... 32

6.13. Internal Error / status signal monitoring register ............................................................................... 35

6.14. Interrupt monitoring .......................................................................................................................... 36

6.15. Multiple camera synchronization Frame Vsync supply .................................................................... 38

6.16. Power On Sequence ........................................................................................................................... 40

6.17. Lock / Re-Lock Sequence ................................................................................................................. 41

7. Absolute Maximum Ratings .......................................................................................................................... 42

8. Recommended Operating Conditions ............................................................................................................ 42

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9. Consumption Current .................................................................................................................................... 43

10. DC Specifications ...................................................................................................................................... 44

10.1. CMOS DC Specifications .................................................................................................................. 44

10.2. CML Receiver DC Specifications ..................................................................................................... 44

10.3. MIPI Transmitter DC Specifications ................................................................................................. 45

10.4. CML Bi-directional Buffer DC Specifications .................................................................................. 46

11. AC Specifications ...................................................................................................................................... 47

11.1. General AC Specifications .................................................................................................................... 47

11.2. CML Receiver AC Specifications ......................................................................................................... 47

11.3. MIPI Transmitter AC Specifications ..................................................................................................... 47

11.4. CML B-directional Buffer AC Specifications ....................................................................................... 47

11.5. 2-wire serial Slave AC Specifications ................................................................................................... 47

12. Package ...................................................................................................................................................... 48

13. Notices and Requests ................................................................................................................................. 49

MIPI is a licensed trademark of MIPI, Inc. in the U.S. and other jurisdictions.

THCV242_ Rev.1.00_E

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5. Pin Description

Pin Name Pin # type* Description

RX0P/N 54, 53 CI V-by-One® HS Input lane0

RX1P/N 57, 56 CI V-by-One® HS Input lane1

RCM0P/N 4, 3 CB CML Bi-directiona Input/Output (Sub-Link).

RCM1P/N 6, 5 CB CML Bi-directiona Input/Output (Sub-Link).

MTX0P/N 22, 21 MO MIPI differential data outputs lane0

MTX1P/N 26, 25 MO MIPI differential data outputs lane1

MTX2P/N 20, 19 MO MIPI differential data outputs lane2

MTX3P/N 28, 27 MO MIPI differential data outputs lane3

MTXCLK0P/N 24, 23 MO MIPI differential clock outputs lane0

MTXCLK1P/N 18, 17 MO MIPI differential clock outputs lane1

RSVDT1L2 13 I2 Reserved Pin, Must be tied to ground for normal operation.

RSVDT2H2 12 I2 Reserved pin. Must be tied to VDDIO2 for normal operation.

PDN 31 I1

Power Down

0: Pow er Dow n Mode

1: Normal Operation

AIN1 37 I1

AIN0 36 I1

SCL 34 B 2-w ire Serial Interface clock line

SDA 35 B 2-w ire Serial Interface data line

GPIO0 40 B General Purpose Input/Output

GPIO1 41 B General Purpose Input/Output

GPIO2 42 B General Purpose Input/Output

GPIO3 43 B General Purpose Input/Output

GPIO4 44 B General Purpose Input/Output

GPIO5 45 B General Purpose Input/Output

GPIO6 46 B General Purpose Input/Output

GPIO7 47 B General Purpose Input/Output

INT0 38 O

INT1 39 O

ERR0 49 O Internal Error / status signal monitoring output

ERR1 50 O Internal Error / status signal monitoring output

EXTSYNC 32 B External Sync input/output for multiple camera syncronization

RSVDL0 59, 60, 62, 63 I0 Reserved Pins, Must be tied to ground for normal operation.

RSVDL2 7, 8, 9, 10, 14 I2 Reserved Pins, Must be tied to ground for normal operation.

VDDIO1 33, 48 P Pow er Supply for CMOS I/O

VDDIO2 2,11 P Pow er Supply for Sub-Link I/O

VDDCORE 1,15,51 P Pow er Supply for Digital Circuit

VDDRX 52,58,64 P Pow er Supply for Analog Circuit

VSSRX 55,61 G GND for Analog Circuit

VDDTX 16,29 P Pow er Supply for Analog Circuit

VDDPLL 30 P Pow er Supply for Analog Circuit

EXPGND 65 G Exposed GND Pad

*type symbol ; MO=MIPI Output, CI=CML Input, CB=CML Bi-directional input/output

I0=1.2v CMOS Input, I1=1.8~3.3v VDDIO1 domain CMOS Input, I2=1.8~3.3v VDDIO2 domain CMOS Input

O=1.8~3.3v VDDIO1 domain CMOS Output, B=1.8~3.3V VDDIO1 domain CMOS Bi-directional input/output

P=Pow er, G=Ground

Device Address Setting for 2-w ire Serial Interface

[AIN1:AIN0]=00: ID=7'h0B

[AIN1:AIN0]=01: ID=7'h34

[AIN1:AIN0]=10: ID=7'h77

[AIN1:AIN0]=11: ID=7'h65

Interrupt signal output.

It must be connected w ith a pull-up resistor.

0 : Interrupt occurred

1 : Steady state

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