xapp592.zip_VHDL/FPGA/Verilog_VHDL_

************************************************************************* ____ ____ / /\/ / /___/ \ / \ \ \/ � Copyright 2012 - 2014 Xilinx, Inc. All rights reserved. \ \ This file contains confidential and proprietary / / information of Xilinx, Inc. and is protected under U.S. /___/ /\ and international copyright and other intellectual \ \ / \ property laws. \___\/\___\ ************************************************************************* Vendor: Xilinx Current readme.txt Version: 2.1 Date Last Modified: 24JUL2014 Date Created: 09AUG2012 Associated Filename: xapp592.zip Associated Document: XAPP592, Implementing SMPTE SDI Interfaces with Kintex-7 GTX Transceivers Supported Device(s): Kintex-7 FPGAs ************************************************************************* Disclaimer: This disclaimer is not a license and does not grant any rights to the materials distributed herewith. Except as otherwise provided in a valid license issued to you by Xilinx, and to the maximum extent permitted by applicable law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and (2) Xilinx shall not be liable (whether in contract or tort, including negligence, or under any other theory of liability) for any loss or damage of any kind or nature related to, arising under or in connection with these materials, including for any direct, or any indirect, special, incidental, or consequential loss or damage (including loss of data, profits, goodwill, or any type of loss or damage suffered as a result of any action brought by a third party) even if such damage or loss was reasonably foreseeable or Xilinx had been advised of the possibility of the same. Critical Applications: Xilinx products are not designed or intended to be fail-safe, or for use in any application requiring fail-safe performance, such as life-support or safety devices or systems, Class III medical devices, nuclear facilities, applications related to the deployment of airbags, or any other applications that could lead to death, personal injury, or severe property or environmental damage (individually and collectively, "Critical Applications"). Customer assumes the sole risk and liability of any use of Xilinx products in Critical Applications, subject only to applicable laws and regulations governing limitations on product liability. THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE AT ALL TIMES. ************************************************************************* This readme file contains these sections: 1. REVISION HISTORY 2. OVERVIEW 3. SOFTWARE TOOLS AND SYSTEM REQUIREMENTS 4. DESIGN FILE HIERARCHY 5. INSTALLATION AND OPERATING INSTRUCTIONS 6. OTHER INFORMATION 7. SUPPORT 1. REVISION HISTORY Readme Date Version Revision Description ========================================================================= 09AUG2012 1.0 Initial Xilinx release. 16OCT2012 1.1 Fixed typos in readme.txt file only. No changes to any other files. 17DEC2012 1.2 Made changes to the DRP controller in the SDI wrapper to insure that it correctly writes to the GTX through the DRP to change the RXCDR_CFG attribute dynamically. Created new GTX wrappers for the demos using v2.4 of the GTX wizard. Version 2.4 of the GTX wizard produces GTX wrappers with a slightly different set of ports, so the demos were updated to match the new GTX wrappers. 10JUL2014 2.0 The GTX wrappers generated by versions 3.0 and later of the transceiver wizard differ in very fundamental ways from wrappers created by earlier versions of the wizard. The SD/HD/3G-SDI core version 3.0 also has some port name changes from earlier versions of the core as required to comply with port naming standards for Xilinx IP. The SDI wrapper files have been updated to support these changes and to align the control logic and wrappers with the GTP and GTH SDI wrappers. All demo files have been updated to match these changes. VHDL versions of wrappers and demos have been removed. And, the app note now targets Vivado only. The code supplied here is compatible with Version 3.3 of the 7 Series FPGAs Transceivers Wizard that ships in Vivado 2014.2. 24JUL2014 2.1 With current Vivado synthesis, the ST 352 payload ID state machine in the SDI RX is susceptible to becoming stuck in an invalid state while the GTX RX is changing between SDI modes. The SDI wrapper has been modified to reset the SDI RX while the GTX RX is changing modes. ========================================================================= 2. OVERVIEW This readme describes how to use the files that come with XAPP592. There are two example SDI designs provided with XAPP592. One design has four SDI receivers and four SDI transmitters. The receivers and transmitters are all independent of each other. The SDI transmitters are driven by video pattern generators. The data received by the SDI receivers is captured by ChipScope Pro modules. The other design is a single channel SDI pass-through configuration where the SDI transmitter retransmits the signal received by the SDI receiver. 3. SOFTWARE TOOLS AND SYSTEM REQUIREMENTS * Vivado 2013.4 or newer 4. DESIGN FILE HIERARCHY The directory structure underneath this top-level folder is described below: \bit_files | This folder contains FPGA configuration bit files for the demos included | in this release. | \chipscope_projects | This folder contains project files for ChipScope Pro analyzer, | one .cpj file for each of the demos included in this release. | \dru | This directory contains the data recovery unit (DRU) code required | to receive 270 Mb/s SD-SDI. The dru.ngc file contains the pre- | synthesized DRU IP. It must be added to the Vivado project along with | the HDL files in the \dru directory. | +--\for_simulation_only | This directory contains a simple model of the DRU that can be | used for simulation. The dru.ngc file cannot be simulated due to | encryption of the file. The simulation model must not, however, | be used in an actual FPGA configuration because it does not have | any jitter tolerance. | \k7gtx_sdi_wrapper | This directory contains the GTX wrapper and GTXE2_COMMON wrapper files | generated by the GTX wizard specifically for these demos. | \kc705_sdi_demo | This directory contains the HDL and other files unique to the quad | SDI demo. | \kc705_sdi_pass_demo | This directory contains the HDL and other files unique to the SDI | pass-through demo. | \kc705_TEDSDI_control | This directory contains the HDL and other files that are used by | both demos to control devices on the KC705 and